Abstract: An information handling system with modular riser components for receiving expansion cards having various requirements. The system includes a riser body assembly having a common support structure for receiving expansion cards. The common support structure may be coupled to different expansion structures to provide support of expansion cards having requirements that would not be met by the common support structure alone.

Abstract: Implementations of the present disclosure are directed to systems and methods for reducing design complexity and critical path timing challenges of credit return logic. A wide bus supports simultaneous transmission of multiple flits, one per lane of the wide bus. A source device transmitting flits on a wide bus selects from among multiple credit return options to ensure that only one of the multiple flits being simultaneously transmitted includes a credit return value. In some example embodiments, the receiving device checks only the flit of one lane of the wide bus (e.g., lane 0) for credit return data. In other example embodiments, the receiving device uses a bitwise-OR to combine the credit return data of all received flits in a single cycle.

Abstract: A signal processing chip includes a plurality of signal processing blocks each configured to transmit and receive a signal via a signal line, samples the signal on the signal line that is transmitted and received by the signal processing blocks, and transmits, to another signal processing chip, a data frame including information indicating the signal sampled at a timing of satisfying a predetermined condition.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device includes a transaction layer generating a transaction packet for transmission of a transaction, a data link layer generating a link packet including a protection code and a sequence number for the transaction packet and a link packet including a sequence number on the basis of the transaction packet, a physical layer generating a physical packet on the basis of the link packet and sequentially outputting the physical packet, a link training module performing negotiation for a link coupled through the physical layer and maintaining data information based on whether a link down occurring when the negotiation for the link is not performed is requested by a host or not, and a PCIe register storing information about the transaction layer, the data link layer, the physical layer, and the link training module.

Abstract: One embodiment of the present invention discloses a two-phase configuration process (“TCP”) to configure a field-programmable gate array (“FPGA”) to include a configurable microcontroller unit (“CMU”) during a phase I configuration and configuring the CMU during a phase II configuration. TCP, in one aspect, is able to receive first configuration data from a first external storage location via a communication bus. After storing the first configuration data in a first configuration memory for configuring FPGA to contain a CMU for the phase I configuration, second configuration data with MCU attributes is obtained from a second external storage location via the communication bus. The second configuration data is subsequently stored in a second configuration memory for programming the CMU for the phase II configuration.

Abstract: The present disclosure advantageously provides a method and system for transferring data over a chip-to-chip interconnect (CCI). At a request node of a coherent interconnect (CHI) of a first chip, receiving at least one peripheral component interface express (PCIe) transaction from a PCIe master device, the PCIe transaction including a stream identifier; selecting a CCI port of the CHI of the first chip based on the stream identifier of the PCIe transaction; and sending the PCIe transaction to the selected CCI port.

Abstract: An optical output device is described that includes one bus system. The bus system includes two bus wires of a bus, two bus units and one bus control unit. The two bus units may include one optical output element one output control unit whose output is connected to the one optical output element a first storage unit for storing address data of the respective bus unit a second storage unit for storing a counter value, a comparison unit whose inputs are connected to the first storage unit and to the second storage unit, and a control unit whose input is connected to an output of the comparison unit and which controls the takeover of data from the bus into the output control unit depending on an output signal or on output data of the comparison unit.

Abstract: A connector connection verification system includes a cable connector and a networking device. The networking device includes a port system defining a port and including a networking device connector, and at least one cable connector sensor device that is located adjacent the port. The cable connector sensor device(s) detects that the cable connector is inserted in the port defined by the port system while the cable connector does not mate with the networking device connector included in the port system and, in response, transmits an incorrect connection signal that indicates that the cable connector is incorrectly connected to the port system. A management interface provided on the networking device may receive the incorrect connection signal from the cable connector sensor device(s), and provide information that describes the cable connector and that indicates that the cable connector is incorrectly connected to the port system for display on a display device.

Abstract: A surgical instrument is disclosed. The surgical instrument includes a first control circuit configured to communicate with an energy module using at least a first protocol over a first communication line and a second control circuit configured to communicate with another surgical instrument coupled to the surgical instrument using at least a second protocol over a second communication line.

Abstract: The present invention describes a method for data transmission between an integrated circuit and an evaluation unit connected to an interrupt pin of the integrated circuit, characterized in that the data transmission is carried out by selectively triggering an atypical interrupt signal or a plurality of interrupt signals composed of regular and/or atypical interrupt signals.

Abstract: A data processing apparatus is provided, that includes communication configured for receiving, from an origin Peripheral Component Interconnect Express (PCIe) device, a translated PCIe packet comprising a destination field that comprises a physical address of a destination PCIe device. Permission circuitry transmits a permission check packet, separate to the translated PCIe packet, to a root port to determine whether the origin PCIe device has permission to access the destination PCIe device. Buffer circuitry stores the translated PCIe packet until a response to the permission check packet is received.

Abstract: In example implementations, a computing device is provided. The computing device includes an expansion interface, a first device, a second device, and a processor communicatively coupled to the expansion interface. The expansion interface includes a plurality of slots. Two slots of the plurality of slots are controlled by a single reset signal. The first device is connected to a first slot of the two slots and has a feature that is compatible with the single reset signal. The second device is connected to a second slot of the two slots and does not have the feature compatible with the single reset signal. The process is to detect the first device connected to the first slot and the second device connected to the second slot and disable the feature by preventing the first slot and the second slot from receiving the single reset signal.

Abstract: An electronic device comprising: a clock pin; at least one data pin; a storage device, configured to store at least one program; a processing circuit, coupled to the clock pin and the data pin. A device ID setting method is performed when the processing circuit executes the program stored in the storage device. The device ID setting method comprises; (a) recording connections between pins between the first electronic device and the second electronic device by the second electronic device; (b) applying the connections as a device ID of the first electronic device by the second electronic device; and (c) setting pins of the first electronic device such that the data pins of the second electronic device are coupled to the data pins of the first electronic device.

Abstract: A system and method for storing data associated with a system management interrupt (SMI) in a computer system. Notification of a system management interrupt is received on a central processing unit. The central processing unit enters a system management mode. A system management handler of a basic input output system (BIOS) is executed by a bootstrap processor of the central processing unit. The system management interrupt is initiated via the bootstrap processor. The system management interrupt data is stored in a register of the bootstrap processor. The SMI data is converted to an accessible format. The converted SMI data is stored in a memory.

Abstract: The present disclosure relates to packing transaction layer (TL) packets at a link layer of a protocol stack. In some examples, channel type data identify a type of message channel for a first TL packet can be generated. A set of slot formats for a slot for packing the first TL packet can be identified based on the channel type data and a slot format database. A respective slot format of the set of slot formats can be selected for the slot based on a message type of the first TL packet, and a message type of a second TL packet. The first TL packet and the second TL packet can be packed into the slot having the selected respective slot format during generation of a link layer packet.

Abstract: A network interface controller (NIC) capable of performing message passing interface (MPI) list matching is provided. The NIC can include a host interface, a network interface, and a hardware list-processing engine (LPE). The host interface can couple the NIC to a host device. The network interface can couple the NIC to a network. During operation, the LPE can receive a match request and perform MPI list matching based on the received match request.

Abstract: Disclosed is a mechanism maintain flow rate limits to flows in a server operating in a single root input/output virtualization (SR-IOV) environment. A transmit pipeline assigns a dedicated transmit queue to a flow. A scheduler allocates a flow transmit bandwidth to the dedicated transmit queue to enforce the flow rate limit. The transmit pipeline assigns the dedicated transmit queue to the flow upon receiving a packet of the flow. A queue identifier (ID) for the dedicated transmit queue is forwarded to a tenant process acting as a source of the flow to support forwarding of packets of the flow to the proper transmit queue. The transmit pipeline maintains security by comparing packet destinations of packets with the destination of the flow associated with the dedicated transmit queue. Packets in the dedicated destination queue with destinations that do not match the flow destination may be dropped.

Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

Abstract: A method for detecting a Direct Memory Access (DMA) memory address violation when testing PCIe devices is disclosed. The method for detecting a DMA memory address violation when testing PCIe devices applies to unintentional and intentional accesses of memory space outside of an area in memory specified by the device driver developed for the device.

Abstract: A network switch includes a data bus, a register, an endpoint controller and a direct memory access controller. The endpoint controller is configured to receive a descriptor generated by a device driver of a host system, store the descriptor in the register, and transfer data between a root complex controller of the host system and the data bus. The descriptor identifies an address of a buffer in a memory of the host system. The direct memory access controller is configured to receive the address of the buffer from the endpoint controller or the register and, based on the address and an indication generated by the device driver, independently control transfer of the data between the memory of the host system and a network device connected to the network switch. The direct memory access controller is a receive direct memory access controller or a transmit direct memory access controller.