Abstract: Distinguishing between snoops initiated internally with respect to a processing unit and snoops initiated externally with respect to a processing unit allows maintenance of cache coherency for a processing unit with multiple independent cache nits. A processing unit with multiple independent cache units, issues an externally initiated snoop to its cache units. Responses from the multiple independent cache units are the basis for a unified response provided to at least the initiator of the external snoop. An internally initiated snoop is communicated to the host system, and communicated to peer cache unit(s) within the processing unit.

Abstract: An ECU includes a microcomputer that has an integrated flash memory. An initial writing flag is set in the microcomputer before an initial writing to the flash memory. The microcomputer enters into a writing mode when the flag determines permission of data writing. When the data-writing to the flash memory is completed, the flag is cleared.

Abstract: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored.

Abstract: A non-volatile semiconductor memory device including: a plurality of cell arrays each having electrically rewritable and non-volatile memory cells arranged therein; a plurality of page buffers disposed in correspondence with the cell arrays respectively for reading and writing data by a page of the respective cell arrays; and a data bus shared by the cell arrays for data transferring between the page buffers and external terminals, wherein the non-volatile semiconductor memory device has a page copy mode defined as follows: read out data of a copy source page within a first cell array to a first page buffer; transfer the read out data to a second page buffer via the data bus; and then write the read out data into a copy destination page of a second cell array.

Abstract: A distributed cache module that allows for a distributed cache between multiple servers of a network without using a central cache manager. The distributed cache module transmits each message with a logical timestamp. The distributed cache module of a server that receives the message will delay forwarding of the message to, for example, a client computer, if preceding timestamps are not received. This insures a correct order of timestamped messages without requiring a central manager to allocate and control the transmission of the messages within the network. Each distributed cache module will request and possibly retrieve data from the cache of another server in response to a file request for the data. The data of a file may be accessed by a plurality of servers joined in a file context.

Abstract: In a semiconductor integrated circuit device equipped with a flash memory and an EEPROM which are nonvolatile memories, the invention provides a technique that makes it possible to restrict an EEPROM capacity to a minimum necessary amount and reduce a chip area. Data of a minimal size required for one application program and rewritten frequently is stored in the EEPROM, and the EEPROM is configured to have a capacity of about that minimal size. Data of the same size that are respectively handled by other applications and rewritten frequently are stored in the flash memory. With respect to an application that is actually used, its data stored in the flash memory is transferred to the EEPROM and used. Data transfer between the flash memory and the EEPROM is performed if necessary. Consequently, the EEPROM capacity can be reduced and chip area reduction can be achieved.

Abstract: A system and method for increasing the throughput of a directory-based storage system is provided. The storage system includes a data storage system to store data signals, and a directory to store state information for the data signals. Requests issued to the storage system are grouped into sets. The requests within a same set are issued in succession to the data storage system to initiate read and/or write memory operations. At the same time, directory entries are read from the directory for each request in the set. Each directory entry is updated as it is retrieved to reflect the requested memory operation. After all directory entries are retrieved, the updated entries are stored back to the directory in succession so that the bi-directional interface to the directory undergoes only a single direction change during the processing of the set.

Abstract: In a disk control system having a RAID controller for continuously writing data on a data stripe composed of a plurality disk apparatus, in response to a write request, data blocks are sequentially written on empty areas of a write target data stripe on the plurality of disks in such a manner that at least one data block is written at a time. Further, in response to the write request, logical addresses having address values prior to address translation are written on logical address log areas on the plurality of disks, as logical-address log information. An upper file system is notified that the write has been completed after the data and the logical-address log information have been completely written.

Abstract: A system and method for efficiently performing memory intensive computations including a bidirectional synchronization mechanism for maintaining consistency of data on which computations will be performed. This can be used to solve various problems such as those in a business context. Synchronization occurs in a near-real-time fashion between data in a database and data stored in memory. The synchronization is accomplished by periodically scanning the database to see if any data has changed. If any data has changed, the changes are copied over to memory so that the data in memory is current. This update is accomplished without copying the entire database into memory each time data in the database changes.

Abstract: CAM-based search engine devices operate to reduce the occurrence of duplicate learned entries within a CAM database when processing search and learn (SNL) instructions. A search engine device may be configured to support processing of first and second immediately consecutive and equivalent SNL instructions as a first SNL instruction and a second search and search instruction, respectively. This processing is performed in order to block an addition of a duplicate learned entry within a database in the search engine device. The search engine device may also be configured to selectively block processing of the second SNL instruction as a second search and search instruction in response to detecting the database as full when the first SNL instruction is processed.

Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.

Abstract: A computer system comprising: a plurality of memories each containing one or more locations; and a first threadlet for causing a first program to run in the computer system when at least one first memory location of the plurality of memory locations is local to the threadlet. Also provided is a method allowing such a threadlet to move itself to memories that include some specified second memory location.

Abstract: A hardware configuration and methodology for serializing or partially serializing WRITE requests directed to a unified data set are subsequently distributed to one or more remote arrays containing a corresponding mirror unified data set. For each unified data set, one of the local disk arrays over which the unified data set is distributed is selected as a supervisor disk array, and a unified sequence number component is included within that supervisor disk array. WRITE requests generated by a local array to mirror unified data set data to a mirror unified data set must be associated with a unified sequence number, and the WRITE requests are therefore serialized or partially serialized by the unified sequence number component. Additional direct communications links are provided between the local arrays over which a unified data set is distributed both to facilitate WRITE-request serialization and to provide a redundant communications paths for added reliability.

Abstract: The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at corresponding nodes, allowing data to be streamed to multiple processes and nodes without regard to synchronization of the plurality of processes. The various nodes may be adaptive computing nodes, kernel or controller nodes, or one or more host processor nodes. The present invention maintains memory integrity, not allowing memory overruns, underruns, or deadlocks. The present invention also provides for “push back” after a memory read, for applications in which it is desirable to “unread” some elements previously read from the memory.

Abstract: The basic idea comprised of the present invention is to provide two sets of descriptors having each at least three descriptors and each set is used in an alternating manner for defining the location of source and target of the copy operations which are to be performed during the defragmentation procedure. The defragmentation procedure is performed as a sequence of copy operations on copy chunks, i.e., a certain number of sequentially arranged bytes to be copied being part of a valid data block to be copied. In each of said copy operations in said sequence the values which are assigned to said descriptors Change. According to a characterizing feature of the present invention during the whole sequence of copy operations comprised of the defragmentation process one of the two sets of descriptors holds information which is usable for restoring the contents of a copy chunk in case of a power break during a copy operation on said copy chunk. Thus, defragmenting is a safe procedure, and data integrity is assured.

Abstract: Apparatus and method to select write transactions and to selectively mark a write transaction with a page closing hint to cause the page in a memory device to which the write transaction is directed to be closed immediately after the write transaction is carried out if no other write transaction is found in a buffer of pending write transactions that is directed to the same rank, bank and page to minimize incidents of incurring lengthy page miss delays.

Abstract: To improve the execution performance of a program which makes indirect array reference by performing data prefetching also on an indirect reference array while reducing an instruction overhead, locality in data reference which cannot be detected by a conventional compiler is enabled to be detected by a user instruction or analysis by a compiler on the basis of a tendency that values of indices in an indirect reference array monotonously increase or decrease. By using the information, issuing of redundant prefetch instructions is suppressed, and data prefetching is enabled to be performed also on an indirect reference array.

Abstract: A storage system is provided that includes a plurality of storage devices and a data structure, accessible to the storage system, that includes a plurality of records corresponding to a plurality of network devices that are coupled to the storage system. Each record includes configuration data that identifies each of the plurality of storage devices to which data access by a respective one of the plurality of network devices is authorized. Each record may further include visibility data that identifies whether certain types of non-data access, such as requests for general information relating to a respective storage device, by a respective one of the plurality of network devices is permitted, even though data access to the respective storage device by the respective one of the plurality of network devices is not authorized.

Abstract: One or more servers are adapted to execute tape application programs. A controller provides communications between the one or more servers and a random access storage device. The controller is configured so that the application programs can concurrently access the random access storage device as a sequential access tape storage device.

Abstract: A method and computer that reduces ABENDs due to end of volume encounters of a job. The method provides an extend-to-new volume processing in response to such encounters. The method permits the definition of primary storage groups and extend storage groups and allows the linking of an extend storage group to a primary storage group. When the job encounters an end-of-volume condition on the current storage volume and is further unable to extend to a new volume in the primary storage group, the method then tries to find a new volume in one or more extend storage groups that are linked to that primary storage group. If no new volume can be found in an extend storage group, an ABEND process is performed.