Abstract: An audio processing integrated circuit chip, such as codec chip, includes at least one port output circuit configured to generate an audio signal to drive an external audio device and a PC beep circuit configured to receive a PC beep signal and to apply the received PC beep signal to an input of the at least one port output circuit. The chip further includes a control circuit configured to detect activity of the PC beep signal and to enable and/or disable the at least one port output circuit responsive to the detected activity.

Abstract: Methods, systems, and computer program products for identifying performance limiting internode data sharing on Non-Uniform Memory Access (NUMA) platforms are provided. A computer-implemented method may include receiving event records collected by a performance monitoring unit (PMU) during event tracing, associating the event records with corresponding operating system information observed during the event tracing, analyzing the event records to identify shared cache line utilization, and generating a shared cache line utilization report in view of the analyzing.

Abstract: A processor of an aspect includes an instruction fetch unit to fetch a pair of instruction order enforcement instructions. The pair of instruction order enforcement instructions are part of an instruction set of the processor. The pair of instruction order enforcement instructions includes an activation instruction and an enforcement instruction. The activation instruction is to occur before the enforcement instruction in a program order. The processor also includes an instruction order enforcement module. The instruction order enforcement module, in response to the pair of the instruction order enforcement instructions, is to prevent instructions occurring after the enforcement instruction in the program order, from being processed prior to the activation instruction, in an out-of-order portion of the processor. Other processors are also disclosed, as are various methods, systems, and instructions.

Abstract: Atomic write operations for storage devices are implemented by maintaining the data that would be overwritten in the cache until the write operation completes. After the write operation completes, including generating any related metadata, a checkpoint is created. After the checkpoint is created, the old data is discarded and the new data becomes the current data for the affected storage locations. If an interruption occurs prior to the creation of the checkpoint, the old data is recovered and any new is discarded. If an interruption occurs after the creation of the checkpoint, any remaining old data is discarded and the new data becomes the current data. Write logs that indicate the locations affected by in progress write operation are used in some implementations. If neither all of the new data nor all of the old data is recoverable, a predetermined pattern can be written into the affected locations.

Abstract: A data access method applicable on an electronic apparatus is provided. The electronic apparatus comprises a control unit, a first storage apparatus, and a second storage apparatus. The method comprising: storing a first part of data and a second part of data of a data group in the first storage apparatus and the second storage apparatus, respectively; and selectively accessing the first storage apparatus and the second storage apparatus via different data paths for the first part of data and the second part of data, wherein access speed to the first storage apparatus is different from access speed to the second storage apparatus.

Abstract: In accordance with one aspect of the present description execution of a particular command by a data processor such as a storage controller, may include obtaining priority over a resource which is also associated with execution of another command, setting a timer for the duration of a dynamically set timeout period, and detecting a potential deadlock condition as a function of expiration of the dynamically set timeout period before execution of the particular command is completed. In one embodiment, the particular command releases priority over the resource upon detection of the potential deadlock condition, and then reobtains priority over the resource in a retry of the command. It is believed that such an arrangement can relieve a potential deadlock condition, allowing execution of one or more commands including the particular command to proceed. Other features and aspects may be realized, depending upon the particular application.

Abstract: An execution unit configured for compression and decompression of numerical data utilizing single instruction, multiple data (SIMD) instructions is described. The numerical data includes integer and floating-point samples. Compression supports three encoding modes: lossless, fixed-rate, and fixed-quality. SIMD instructions for compression operations may include attenuation, derivative calculations, bit packing to form compressed packets, header generation for the packets, and packed array output operations. SIMD instructions for decompression may include packed array input operations, header recovery, decoder control, bit unpacking, integration, and amplification. Compression and decompression may be implemented in a microprocessor, digital signal processor, field-programmable gate array, application-specific integrated circuit, system-on-chip, or graphics processor, using SIMD instructions. Compression and decompression of numerical data can reduce memory, networking, and storage bottlenecks.

Abstract: A display apparatus and a control method thereof are provided. The display apparatus includes: a communication interface configured to receive a video signal by using a preset setting value; a sensor configured to generate a test signal for checking whether the display apparatus is abnormal in order to sense an abnormality of the display apparatus; a controller configured to adjust a setting value of the communication interface in response to an abnormality of the display apparatus not being sensed; and a display configured to display the video signal received by the communication interface, the setting value of which has been adjusted.

Abstract: Scheduling a proposed additional data transfer from one or more source storage devices to one or more target storage devices. A computer receives a request for the proposed additional data transfer, and in response, determines a measure of the proposed additional data transfer. The computer determines a measure of recent actual data transfers. The recent actual data transfers involve one or more of the source storage devices and one or more of the target storage devices. In response to the request for the proposed additional data transfer, the computer estimates performance of one or more of the source storage devices and one or more of the target storage devices that would occur during the proposed additional data transfer based on the measure of recent actual data transfers combined with the measure of the proposed additional data transfer.

Abstract: A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units, and a memory control circuit unit and the memory storage apparatus are provided. The method includes: grouping the physical erasing units into at least a data area and a spare area; configuring a plurality of logical units for mapping to the physical erasing units of the data area; and dynamically reserving a predetermined number of physical erasing units dedicating to write sequential data. Accordingly, the method can fast write the sequential data with the page-based memory management.

Abstract: A memory module includes a first storage module including a first module controller and a first memory unit. The first storage module is configured to receive first partial data from a host and write the first partial data to the first memory unit. A second storage module includes a second module controller and a second memory unit. The second storage module is configured to receive second partial data from the host and write the second partial data to the second memory unit. The first storage module and the second storage module are configured to connect to the host through a single host interface bus.

Abstract: Digital data, including audio and video, may be communicated at increased data rates by utilizing non-data signal channels in cables to communicate additional data. For data transmission, a reformatter receives data in a first format adapted for communication over the data signal channels of a cable. The reformatter may convert the received data into a second format with one or more additional data signals. The reformatter then utilizes non-data signal channels of the cable to carry the additional data signals. An example non-data signal channel may include a clock signal channel, and the reformatter may fold a clock signal into one or more of the data signals to allow for clock recovery downstream. Data may also be split into two or more subsets and each subset encoded separately, for example with two or more data encoders such as legacy HDMI encoders.

Abstract: A method includes providing access to a multi-panel display including a plurality of display panels. Each panel of the plurality of display panels is mounted onto a mechanical support structure. The method further includes identifying a defective panel from the plurality of display panels. Without powering down the multi-panel display, electrical connection to the defective panel is disconnected and the defective panel is removed from the mechanical support structure. The method also includes attaching a replacement display panel to the mechanical support structure at the location of the defective panel, and connecting power to the replacement display panel. One or more of the remaining of the plurality of display panels continue to display during the time the defective panel is disconnected and removed, and the replacement display is attached.

Abstract: An apparatus and method are provided for transmitting and receiving data in a data communication system. The method includes receiving certain multimedia data from a portable terminal using a first data communication scheme; transmitting the certain multimedia data to an external device; receiving control data corresponding to the certain multimedia data from the external device based on the first data communication scheme; converting the control data into a data format of a second data communication scheme; generating data including the converted control data; and transmitting the data to the portable terminal.

Abstract: Embodiments of the present invention relate to integrated modular display systems. In one embodiment, a modular multi-panel display system includes a mechanical support structure, and a plurality of LED display panels detachably mounted to the mechanical support structure so as to form an integrated display panel. Each LED panel includes an LED array and an LED driver coupled to the LED array. Each panel further includes a power supply unit disposed outside the housing and electrically coupled to the receiver circuit. The mechanical structure is configured to provide mechanical support to the plurality of LED display panels without providing hermetic sealing. Each of the plurality of LED display panels is hermetically sealed.

Abstract: A tablet computer is provided, which includes a sensor section operable to detect positional input by a human operator and output a positional input signal; a display, laid over the sensor section, operable to receive and display a video signal; and a processor, coupled to a memory storing programs for running an operating system (OS) and executing software loaded to the memory, the processor being operable to receive and process the positional input signal from the sensor section and to output a video signal of the OS and the software to the display. The tablet computer further includes a sensor signal filter capable of selectively communicating the positional input signal from the sensor section to the processor, to a separate external processor, or to neither the processor nor the separate external processor; and a display switch capable of coupling the display to the processor or to the separate external processor.

Abstract: Systems and methods are described herein that include flow control mechanisms that provide a receiving device with the ability to reclaim buffers that have been previously advertised to a sending device. Data structures and communication methods are described that facilitate the communication of flow control messages between sending and receiving devices that allow an advertised window to be reduced, and buffers to be released, by a sending device in response to a flow control message from the receiving device.

Abstract: Techniques are described for enabling a virtual machine to be presented with an amount of available guest memory, where a hypervisor or other privileged component manages the mapping of the resources based at least in part on the capacity of resources one or more hosts. This enables resources to be effectively oversubscribed to on host computing devices that have a limited amount of total available resources but which are running multiple virtual machines. For example, each virtual machine on the device can be presented as having access to the total amount of available resources that are available on the device or more in some cases. In some cases, resources may be mapped to a plurality of hosts that have available resources.

Abstract: A simplified coherency controller supports multiple exclusively active fully coherent agent interfaces and any number of active I/O (partially) coherent agent interfaces. A state controller determines which fully coherent agent is active. Multiple fully coherent agents can be simultaneously active during a short period of a transition of processing from one to another processor. Multiple fully coherent agents can be simultaneously active, though without a mutually consistent view of memory, which is practical in cases such as when running multiple operating systems on different processors.

Abstract: An integrated circuit device comprises at least one digital signal processor, DSP, module, the at least one DSP module comprising a plurality of data registers and at least one data execution unit, DEU, module arranged to execute operations on data stored within the data registers. The at least one DEU module is arranged to, in response to receiving an extreme value index instruction, compare a previous extreme value located within a first data register set of the DSP module with at least one input vector data value located within a second data register set of the DSP module, and determine an extreme value thereof. The at least one DEU module is further arranged to, if the determined extreme value comprises an input vector data value located within the second data register set, store the determined extreme value in the first data register set, determine an index value for the determined extreme value, and store the determined index value in the first data register set.