Abstract: An implementation of an ISDN router enables computers interconnected to each other and to the ISDN to share resources by issuing operating system commands. One computer can access a storage disk or other resource of another computer distributed at any terminal location on the ISDN. Each disk on the Network has a unique name by which it is accessed. The configuration of the Network and number of computers distributed on it are transparent to each user. To improve bandwidth utilization of the ISDN line while sharing terminal resources, a B-channel allocation algorithm executed by routers between the terminals and the ISDN line dynamically allocates bandwidth by monitoring traffic at each destination queue and in response allocating or deallocating virtual B-channels. Bandwidth utilization is optimized by packaging data packets into trains that are transmitted to the destination when the train is completed and upon satisfaction of other conditions.

Abstract: A personal computer or workstation on a network includes a quick-choice cache into which are collected the names and aliases of networked devices or services that are expected to be most routinely used by a particular user. The cache is initialized to contain the names and aliases of devices within a network zone assigned to the workstation. This collection of names/aliases is expanded each time the user makes a connection to a device not previously listed. The cache drives a graphic user interface (GUI) that shows the user what service categories are available within the cache, and then when a service category is selected, what specific devices are included within the cache under that service category. The GUI permits quick logical connection to devices whose aliases are stored in the user's cache. A connection map later graphically shows the user what connections he or she has made.

Abstract: A multi-processor data processing system (10) includes an array (12) of one or more data processors (50-65). Data processing system (10) has edge interface circuits (14,16) for transferring control and data to and from the array (12). A data bus (32), an address bus (34), and a control bus (36) each transfers information to and from the array (12), the edge interfaces (14,16), and a bus interface controller (22). In an alternate embodiment, multi-processor data processing system (210) includes an array (212) of one or more data processors (250-258). Data processing system (210) has edge interfaces (214-217) for transferring control and data to and from the array (212). A data bus (232), an address bus (234), and a control bus (236) each transfers information to and from the array (212), the edge interfaces (214-217), and a bus interface controller (222).

Abstract: The present invention discloses a multistream instruction processor issuing instructions from N instruction streams in parallel, and processing instruction streams interchangeably when the number of the instruction streams is N or larger than N.

Abstract: A high-availability computer system comprises at least two processors, each having its own private disk drive, and a shared disk drive, accessible by both processors. Each of the private disk drives holds system files for establishing a processor as a secondary processor, and the shared disk drive holds system files for establishing a processor as a primary processor. When it boots up, each processor decides whether to use the system files from its private disk so as to become a secondary, or to use the system files from the shared disk so as to become the primary. As as result, after a system failure or reboot, either processor can pick up the characteristics of the the primary processor, and will have all the most up-to-date primary information available to it.