Patents Examined by Krista Soderholm
  • Patent number: 8198716
    Abstract: Methods and apparatus to provide die backside connections are described. In one embodiment, the backside of a die is metallized and coupled to another die or a substrate. Other embodiments are also described.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: June 12, 2012
    Assignee: Intel Corporation
    Inventors: Shanggar Periaman, Kooi Chi Ooi, Bok Eng Cheah, Yen Hsiang Chew
  • Patent number: 8183700
    Abstract: Many holes are formed in an interlayer insulating film and the surface of the interlayer insulating film is covered with a metal film, with its surface undulated by openings or recesses formed to scatter reflection light. The size of the recesses is about the size of contact holes of elements. Hence the recesses are not detectable by an image recognition apparatus. The size of the metal film, however, is set so that it can be detected by the image recognition apparatus.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: May 22, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Mutsuo Nishikawa, Kazuhiko Ikoma
  • Patent number: 8183680
    Abstract: Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages are described. A die-up or die-down package includes an IC die, a die attach pad, a heat spreader cap coupled to the die attach pad defining a cavity, and one or more peripheral rows of leads surrounding the die attach pad. The leads do not protrude substantially from the footprint of the encasing structure. The die attach pad and the heat spreader cap defines an encasing structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The encasing structure also dissipates heat generated by the IC die during operation.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: May 22, 2012
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan
  • Patent number: 8174115
    Abstract: Provided is a multi-chip package memory device. The multi-chip package memory device may include a transmission memory chip and a plurality of memory chips that are stacked on the transmission memory chip. The transmission memory chip may include a temporary storage unit, and may transmit a received command or received data to a corresponding memory chip, or to an external element. Each of the memory chips may include a memory core, and may delay the received command according to the properties of the memory chips and then may output delay commands. The transmission memory chip may store the received data in different portions of the temporary storage unit when the delay commands are respectively received.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: May 8, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hoe-Ju Chung
  • Patent number: 8167552
    Abstract: A locking member for a device for fastening ring sectors to an aircraft turbine engine casing is disclosed. The member has first and second clamping branches, which are connected together by curving joining portions, via a connecting branch. The joining portion of center thickness E1 has an inside surface of mean radius Rm1, and the joining portion of center thickness E2 has an inside surface of mean radius Rm2. Thickness E1 is strictly smaller than thickness E2, and mean radius Rm1 is strictly smaller than mean radius Rm2.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: May 1, 2012
    Assignee: Snecma
    Inventors: Serge Louis Antunes, David Da Silva
  • Patent number: 8154101
    Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: April 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharkar, Binghua Hu
  • Patent number: 8147186
    Abstract: A centrifugal compressor having a wide operating range, being economically efficient and high reliability in terms of a stable operation is provided. A centrifugal compressor including a partition wall for dividing a flow channel in the diffuser section and the volute section into a plurality of channels in the direction of circulation of the fluid so as to define a hub-side flow channel and a shroud-side flow channel; and a flow rate adjusting valve for lowering the flow rate of the fluid flowing in the shroud-side flow channel to increase the flow rate in the hub-side flow channel when the flow rate of the fluid compressed by an impeller is low and not lowering the flow rate of the fluid flowing the shroud-side flow channel to allow the fluid to flow both in the shroud-side flow channel and the hub-side flow channel when the flow rate of the fluid compressed by the impeller is high is employed.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: April 3, 2012
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Seiichi Ibaraki, Isao Tomita, Yasuaki Jinnai, Takashi Shiraishi, Koichi Sugimoto
  • Patent number: 8142142
    Abstract: A gas turbine transition duct apparatus is provided comprising first and second turbine transition ducts and a strip seal. The strip seal may comprise a sealing element and a spring structure.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: March 27, 2012
    Assignee: Siemens Energy, Inc.
    Inventors: James M. Zborovsky, Andreas J. Heilos
  • Patent number: 8138026
    Abstract: A leadframe with a structure made of a base metal (105), wherein the structure has a plurality of surfaces. On each of these surfaces are metal layers in a stack adherent to the base metal. The stack comprises a nickel layer (201) in contact with the base metal, a palladium layer (202) in contact with the nickel layer, and an outermost tin layer (203) in contact with the palladium layer. In terms of preferred layer thicknesses, the nickel layer is between about 0.5 and 2.0 ?m thick, the palladium layer between about 5 and 150 nm thick, and the tin layer less than about 5 nm thick, preferably about 3 nm. At this thinness, the tin has no capability of forming whiskers, but offers superb adhesion to polymeric encapsulation materials, improved characteristics for reliable stitch bonding as well as affinity to reflow metals (solders).
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: March 20, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Donald C Abbott
  • Patent number: 8133003
    Abstract: Disclosed is a seal for a turbomachine including at least one fixed component located proximate to a rotating component of the turbomachine defining a clearance therebetween. At least one magnet is located at the at least one fixed component. The at least one magnet is, when activated, capable of moving the at least one fixed component thereby adjusting the clearance between the fixed component and the rotating component. Further disclosed is a turbomachine utilizing the seal and a method for adjusting a position of at least one fixed component of a turbomachine.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: March 13, 2012
    Assignee: General Electric Company
    Inventors: Michael Alan Davi, David Andrew Stasenko
  • Patent number: 8120156
    Abstract: The present invention provides an integrated circuit package system with die on base package comprising forming a base package comprising, forming a substrate, mounting a first integrated circuit on the substrate, encapsulating the integrated circuit and the substrate with a molding compound, and testing the base package, attaching a bare die to the base package, connecting electrically the bare die to the substrate and encapsulating the bare die and the base package.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: February 21, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 8120148
    Abstract: A package structure with an embedded die includes a core layer, a first build-up wiring structure, and a second build-up wiring structure. The core layer has a first surface and a second surface opposite thereto. Besides, the core layer includes a first dielectric layer, a leadframe, a die, a first signal layer, and a second signal layer. The die is disposed on and electrically connected to the leadframe. The die and the leadframe are embedded in the first dielectric layer. The first signal layer is disposed on an upper surface of the first dielectric layer and electrically connected to the leadframe. The second signal layer is disposed on a bottom surface of the first dielectric layer and electrically connected to the leadframe. The first and the second build-up wiring structures are disposed on the first and the second surfaces of the core layer, respectively.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: February 21, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo-Hua Chen, Ying-Te Ou, Chieh-Chen Fu
  • Patent number: 8106489
    Abstract: A package and packaging method are provided that enable packaging of larger dies and/or smaller packages. Generally, the method includes steps of: (i) reducing a thickness of a portion of a top surface of leads of a leadframe extending into a package being formed; (ii) mounting a die to a paddle of the leadframe, the die extending past an edge of the paddle into a space created by reducing the thickness of the leads; and (iii) encapsulating the die and leadframe, including the reduced portion of the leads, in a molding compound. In one embodiment, the leads are reduced by half-etching the portion of the top surface. Preferably, the method further includes wire bonding pads on the die to etched portions of the leads to electrically couple the die to the leads. Alternatively, wire bonding is between the pads and non-etched portions of the leads. Other embodiments are also disclosed.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: January 31, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Carlo Gamboa, Salvador Padre
  • Patent number: 8102049
    Abstract: The present invention provides a semiconductor device including at least one of an insulating layer and a semiconductor layer each including a hole formed therein, and a through electrode provided in the hole. In the semiconductor device, the side wall of the hole is constituted of a first region from the opening of the hole to a predetermined position between the opening of the hole and the bottom surface of the hole, and a second region from the predetermined position to the bottom surface of the hole. The through electrode includes a seed layer and a plating layer. The seed layer covers the second region and the bottom surface of the hole without covering the first region. In addition, the plating layer covers the seed layer and at least a part of the first region.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: January 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuaki Takahashi, Masahiro Komuro, Koji Soejima, Satoshi Matsui, Masaya Kawano
  • Patent number: 8093703
    Abstract: In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: January 10, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pyoung-Wan Kim, Teak-Hoon Lee, Chul-Yong Jang
  • Patent number: 8092153
    Abstract: A gas turbine engine has a plurality of radial struts in a bypass duct. At least one strut has a scoop incorporated with the fairing of the strut and in communication with an air passage of an engine secondary air system. The scoop faces a bypass air flow to scoop a portion of the bypass air flow using available dynamic pressure in the bypass duct. Scooped air may be provided, for example, to an active tip clearance control apparatus in a long duct turbofan engine.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: January 10, 2012
    Assignee: Pratt & Whitney Canada Corp.
    Inventors: Steven Strecker, Hong-Wei Hui
  • Patent number: 8083492
    Abstract: Turbo-engine which has a low-pressure area, containing at least one shaft, wherein the low-pressure area has an inflow area, the shaft having, at least on its inflow part arranged in the inflow area, a heat resistant material, wherein the shaft has, on outflow parts arranged opposite the inflow part, a 26NiCrV14-5 and/or 2SNiCrMoVii-5 and/or 22CrNiM09-9 material.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: December 27, 2011
    Assignee: Siemens Aktiengesellschaft
    Inventor: Torsten-Ulf Kern
  • Patent number: 8080876
    Abstract: A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, John U. Knickerbocker, Michelle L. Steen, Cornelia K. Tsang
  • Patent number: 8063485
    Abstract: A board mounted integrated electronics package assembly is provided with one or more securing elements to attach a heat dissipating device directly to the package. The securing element(s) is located along a periphery of the package and anchors a base of the heat dissipating device to the package, thereby eliminating employment of a secondary heat dissipating material between the package and the heat dissipating device.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: November 22, 2011
    Assignee: Advanced Thermal Solutions, Inc.
    Inventor: Kaveh Azar
  • Patent number: 8052397
    Abstract: A rotor and shaft assembly for turbomachinery has a polygon shaped drive collar interposed between corresponding polygonal mating surfaces of a drive shaft and a rotor hub. The mating surfaces of the polygon collar, the drive shaft and the rotor hub may be sized both axially and radially for required torque transmission without the need for hub inserts or oversized shafts. The polygon drive collar is manufacturable using standard machine tools such as lathes and end mills that remove metal in a tool path following not more than two axes of simultaneous movement. A shaft end assembly secures the rotor and drive collar to the shaft.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: November 8, 2011
    Assignee: Lawrence Pumps Inc.
    Inventor: Mark Thomas Corcoran