Abstract: A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system. Multiple processors are grouped together into four or more physically separable clusters, each cluster having a common cluster shared memory that is symmetrically accessible by all of the processors in that cluster; however, only some of the clusters are adjacently interconnected. Clusters are adjacently interconnected to form a floating shared memory if certain memory access conditions relating to relative memory latency and relative data locality can create an effective shared memory parallel programming environment. A shared memory model can be used with programs that can be executed in the cluster shared memory of a single cluster, or in the floating shared memory that is defined across an extended shared memory space comprised of the cluster shared memories of any set of adjacently interconnected clusters.

Abstract: Generation of functional status followed by the use of the status to control the sequencing of microinstructions is a well known critical path in processor designs. The delay associated with the path is exacerbated in superscalar machines by the additional statuses that are produced by multiple functional units from which the appropriate status must be selected for controlling the sequencing of microinstructions. This is especially true in horizontally microcoded machines. The adverse affects on the delay can be reduced by using a staged multiplexor design. For the staged multiplexor to be useful, all functional unit status should be produced as early as possible. In this invention, a status predictor is described that allows the status associated with the shifter to be generated directly from the inputs to the shifter.

Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.

Abstract: A RISC architecture computer configured for emulating the instruction set of a target computer to execute software written for the target computer, e.g., an Intel 80X86, a Motorola 680X0 or a MIPS R3000. The apparatus is integrated with a core RISC computer to form a RISC computer that executes an expanded RISC instruction. The expanded RISC instruction contains data fields which designate indirect registers that point to emulation registers that correspond to registers in the target computer. The width of the emulation registers is at least the width of those in the target computer. However, a field in the expanded RISC instruction restricts the emulated width to that required by a particular emulated instruction. Additionally, the expanded RISC instruction contains a field which designates the emulation mode for condition codes and selects logic to match the condition codes of the target computer.

Abstract: A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

Abstract: A method and apparatus for handling resource allocation during processor stall conditions. The instruction issue components of a processor are stalled (e.g., the issuance of new instruction is frozen) as a result of various stall conditions. One stall condition (full stall) occurs when an allocated buffer resource becomes full. Another stall condition (partial stall) occurs during register renaming and a given instruction sources a larger register width than the register alias table currently contains within the RAT buffer. This is a partial width data dependency and a partial stall is asserted. The present invention, upon detection of a full stall, does not allocate any buffer entries within the clock cycle that causing the full stall and resource pointers are not advanced and instructions issued during that clock cycle are not allocated. Within the clock cycle of the deassertion of the full stall, the resource buffers are allocated and the resource allocation pointers are updated.

Abstract: A scalable register file including first and second micro-register files organized in a pipelined fashion to minimize the access time of the register file where there are a large number of registers or multiple functional units. Interposed between the first and second micro-register files are a first plurality of pipeline registers for storing the register contents fetched from the first micro-register file during a first pipeline cycle. A second plurality of pipeline registers are coupled to the second micro-register files for storing the register contents fetched from the second micro-register file during a second pipeline stage and those registers being stored in the first plurality of pipeline registers. The first plurality of pipeline registers are coupled to the bit lines of the second micro-register file.

Abstract: A slave mode/master mode switching flag, a switch 19, and a start bit 0/1 generator 20 are provided in a two-way communication device 1 incorporated in a microcomputer. In a slave mode, data transmission and reception are synchronized with a start bit over a communication line, and the communication device does not output a start bit for transmission. In a master mode, data transmission is synchronized with a start bit outputted from the communication device, and data reception is synchronized with a start bit over the communication line. The communication device outputs a start bit for communication data. Two-wire two-way serial communication is effected by combining microcomputers set at a master mode. Single-wire two-way serial communication is effected by combining a microcomputer set at a master mode and another microcomputer set at a slave mode.

Abstract: A program is translated by automatically generating a flowgraph, using the flowgraph to analyze the program to provide information about blocks of instructions in the flowgraph, and then using the flowgraph and the information about the blocks of instructions to generate translated instructions. Due to execution transfers to computed destination addresses that are not determined prior to program execution, it is not possible to include all of the program instructions in the flowgraph. Execution transfers to these computed destinations are coded as calls to an interpreter that interprets the untranslated code. Returns from the interpreter are made to block entry points. Moreover, information about the location of untranslated instructions in an original program is discovered during execution of a partial translation of the program, and that information is used later during re-translation of the original program.

Abstract: A carry-save adder for use in a binary multiplier with a reduced number of full adder stages. The carry-save adder is for summing columns of binary data and is implemented with a plurality of one-bit and two-bit full adders. The one-bit and two-bit full adders are configured in a plurality of interconnected modified Wallace-Tree adders, each modified Wallace-Tree adder for summing binary data bits from one or more columns and generating a partial sum and a partial carry. Each modified Wallace-Tree adder has a plurality of stages comprising a combination of one-bit and two-bit full adders for reducing the number of the binary data bits, the last stage comprising a single one-bit full adder for generating the partial sum and partial carry results. A plurality of conductors interconnects the stages of each modified Wallace-Tree adder with stages in the same modified Wallace-Tree adder and with stages in other modified Wallace-Tree adders.

Abstract: A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively.

Abstract: A system for and method of operating of data communication interface for handling communication between a data processing system and a plurality of communication channels is disclosed. The method provides for monitoring posting of actions from the data processing system and from the plurality of communication channels. Responsive to detection of posting of an action, it is determined if the action was posted by the data processing system. Where the action was posted from the data processing system, it is determined if conditions permit the action to be executed. Responsive to an affirmative determination that the action can be executed it is executed. Responsive to a determination that the action was posted from the host data processing, but was not executable, the action is added to the end of a queue of actions. The first entry in the queue is then examined for executability. If executable, the first action is executed and replaced as first action with the next action from the queue, if any.

Abstract: A method and apparatus for allocating a number of vacant entries of a buffer resource and generating a set of enable vectors based thereon for a set of issued instructions. A deallocation vector of a reservation station is searched in order to locate, within one clock cycle, the vacancies within the reservation station for storage of instruction information associated with several issued operations. Vacancies are indicated by bits of the deallocation vector. A general static and dynamic approach are disclosed for performing the vacant entry identification at high speed within a single clock cycle. Alternate embodiments are disclosed, based on the general approach, that divide the deallocation vector into separate portions (consecutive bits or interleaved) and process each portion based on the general approaches. Rotating priority reference points within the deallocation vector may be used to vary the starting point for vacancy location.

Abstract: The present invention is directed to an integrated data processing system that includes a general purpose (GP) CPU core for processing data in accordance with a GP instruction set and a digital signal processor (DSP) module for processing data in accordance with command-list code. The DSP module is operable to execute the command-list code independent of and in parallel with execution of the GP instruction set by the CPU core. The system also includes a mechanism for DTMF detection.

Abstract: A microprocessor partially decodes instructions retrieved from main memory before placing them into the microprocessor's integrated instruction cache. Each storage location in the instruction cache includes two slots for decoded instructions. One slot controls one of the microprocessor's integer pipelines and a port to the microprocessor's data cache. A second slot controls the second integer pipeline or one of the microprocessor's floating point units. The instructions retrieved from main memory are decoded by a loader unit which decodes the instructions from the compact form as stored in main memory and places them into the two slots of the instruction cache entry according to their functions. In addition, auxiliary information is placed in the cache entry along with the instruction to control parallel execution as well as emulation of complex instructions.

Abstract: A distributed computing system using a data communications network may have a number of service providers for a given service or remote procedure call. A client on the network makes reference to a name service to obtain the network address of one of these service providers. The name service maintains for each client or group of clients a configuration profile of the service providers in order to resolve the issue of selecting one of the several service providers when a request is made. A single configuration profile is a priority-ordered search list that maps from a service identifier (e.g., remote procedure call interface specification) into service provider (e.g., remote procedure call server) names. A configuration profile may include names for individual service providers, and/or named groups of service providers, and/or other configuration profiles. Configuration profiles are stored in a manner that makes them accessible throughout the distributed system, e.g., in the name service.

Abstract: An asynchronous computer bus providing transfers of data on consecutive processor clock cycles. The bus comprises consecutive data transfer commence indication means, starting address transmission means, consecutive data transfer indication means, and data transmission means. The invention provides for the "burst" capabilities of modern processors wherein entire blocks of data are transmitted within a single request.

Abstract: A logical operation method for evaluating a train of output data to be obtained when a plurality of input patterns are successively applied to a memory element whose output value depends upon a sequence of input values. For each of the plurality of patterns in time series, the method decides whether or not the pertinent pattern is a holding pattern which means that the output value of the memory element depends upon a preceding pattern. Subsequently, the method evaluates a first train of data which consists of flags each indicating whether or not the respective pattern is the holding pattern, and a second train of data which consist of a predetermined logical values for the holding patterns and output logical values of the memory element for the non-holding patterns. Finally, the method subjects the first and second trains of data to operations in parallel by the use of a parallel arithmetic unit, thereby obtaining the train of output data of the memory element in parallel.

Abstract: A parallel processor system which includes a plurality of processors each for executing at least one of a plurality of mutually associated programs and a transfer circuit. The transfer circuit is connected to the processors, and is provided for transferring the data outputted from any one of the programs during execution of one program by any one of the processors to other processors to which a receiving program is allotted. The transfer operation is performed in response to a program identification code outputted during execution of the one program by one processor to identify the receiving program.

Abstract: In a system for displaying prices in a retail store, improved system architecture and stored programs are disclosed to permit improved accuracy in confirming the physical location of display devices called labels. A response from a label to the host, or central computer, has appended to it an additional message by an appender, one of a plurality of appenders located throughout the architecture. The appender's message permits localization of the labels. A power-on status flag in a response from the labels permits the central computer to determine, through global inquiries to all the labels, whether any of the labels has had an interruption of power. A dongle or RF-linked bar-code scanner permits store personnel to send messages to the central computer to request that labels in a particular subarea of the store display alternative information such as the amount of inventory for items in that subarea.