Patents Examined by Lah Vinh
  • Patent number: 10672622
    Abstract: An etching method includes loading, first and second supplying, removing and etching steps. In the loading step, a target object is loaded into a chamber. In the first supply step, a first gas containing carbon, hydrogen and fluorine is supplied into the chamber. In the modification step, plasma of the first gas is generated to modify a surface of a mask film and a surface of an organic film which is not covered with the mask film. In the second supply step, a second gas for etching the organic film is supplied into the chamber. In the removal step, a modified layer formed on the surface of the organic film is removed by applying a first high frequency bias power. In the etching step, the organic film below the modified layer is etched by applying a second high frequency bias power lower than the first high frequency bias power.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 2, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusuke Shimizu, Akinori Kitamura, Masahiko Takahashi
  • Patent number: 10147619
    Abstract: A substrate treatment apparatus according to an embodiment includes a treatment part, a cyclic path, a heater, and a first injector. The treatment part is supplied with an etchant containing phosphoric acid and a silica deposition suppressor, and brings a substrate having a silicon nitride film on a surface thereof into contact with the etchant to remove the silicon nitride film from the substrate. The cyclic path circulates the etchant in the treatment part. The heater heats the etchant. The first injector is provided on the cyclic path, and injects the silica deposition suppressor into the etchant.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: December 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsuhiro Sato, Kaori Deura, Yoshinori Kitamura, Takahiro Terada, Yoshihiro Ogawa, Yuji Hashimoto, Masaaki Hirakawa, Yukako Murakami, Hideaki Hirabayashi
  • Patent number: 9190287
    Abstract: In fin FET fabrication, side walls of a semiconductor fin formed on a substrate have certain roughness. Using such fins having roughness may induce variations in characteristics between transistors due to their shapes or the like. An object of the present invention is to provide a fin FET fabrication method capable of improving device characteristic by easily reducing the roughness of the side walls of fins after formation. In one embodiment of the present invention, side walls of a semiconductor fin are etched by an ion beam extracted from a grid to reduce the roughness of the side walls.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: November 17, 2015
    Assignee: Canon Anelva Corporation
    Inventors: Takashi Nakagawa, Masayoshi Ikeda, Yukito Nakagawa, Yasushi Kamiya, Yoshimitsu Kodaira
  • Patent number: 8389418
    Abstract: The present disclosure relates to a solution for selectively removing metal, such as Ta or TaN, from a substrate, such as an aluminum containing substrate. The solution comprises an acid, such as HF or buffered HF, an ingredient comprising a fluorine ion, such as ammonium fluoride (NH4F), ethylene glycol, and water. A method of selectively removing metal from a substrate using this solution is also disclosed.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: March 5, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Jeremy W. Epton, John Deem
  • Patent number: 7591958
    Abstract: The manufacturing of electronic components on individual substrates made of an insulating material includes molding, in a silicon wafer, an insulating material with a thickness corresponding to the final thickness desired for the substrates, manufacturing the electronic components, and removing the silicon from the rear surface of the wafer after manufacturing of the components.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: September 22, 2009
    Assignee: STMicroelectronics SA
    Inventors: Pascal Gardes, Fabrice Guitton