Abstract: The invention may relate to a digital to analog converter. The digital to analog converter may comprise a plurality of controllable current sources and a control circuit. The plurality of controllable current sources may include a first and a second controllable current source. Each of the plurality of controllable current sources may be controllable between a first state and a second state. The control circuit may be coupled to the plurality of controllable current sources. The control circuit may be configured to control digital to analog conversion at a sampling interval. The control circuit may be configured to control a first state transition of the first controllable current source at a timing in the sampling interval different from a second state transition of the second controllable current source.

Abstract: A method, apparatus and computer program product for encoding data transmitted over a communications channel, including pre-loading an encoder dictionary with a set of character strings expected to appear in input data to be encoded; and encoding the input data with the set of expected character strings pre-loaded in the encoder dictionary. In another aspect, there is provided a method, apparatus and computer program product for decoding encoded data received over a communications channel, including pre-loading a decoder dictionary with a set of character strings expected to appear in the encoded data; and decoding the encoded data with the set of expected character strings pre-loaded in the decoder dictionary.

Abstract: In a multiturn rotary encoder, a first code disk is arranged with an input shaft for detecting the angular position of the input shaft within one rotation. To detect the number of rotations of the input shaft, a multiturn part is provided with further code disks in the form of magnet bodies which are driven geared down. A printed circuit board having detector devices for scanning the first code disk and the magnet bodies is positioned between the first code disk and the multiturn part. The detector devices of the first code disk and of the magnet bodies are mounted on one common side of a printed circuit board which is opposite the first code disk.

Abstract: Line drivers are provided that are suitable for driving communication cables (e.g., in Data Over Cable Service Interface Specification (DOCSIS) certified systems) without the need for output drivers and their size, power-consumption, noise and signal-distortion penalities. These line drivers directly couple switched current mirrors to a transformer's input winding to simultaneously provide currents in response to a differential input signal and a digital command signal and drive the load impedance to thereby realize a corresponding signal gain.

Abstract: Differential heating is avoided by a digital to analog converter for generating analog cyclical waveforms having a period. The cyclical waveforms are generated by conversion of a sequence of step wise linearly incrementing digital phase words presented during the period for conversion. The digital to analog converter has a clock for operating conversion timing within the digital to analog converter. The clock generates a clock pulse for conversion of each of the digital phase words by said digital to analog converter while generating the cyclical waveform. A lookup read only memory for converting each of the incrementing digital phase words within the period into a plurality of ON commands to be used by a plurality of current sources. The plurality of ON commands are timed to generate the cyclical waveforms and have nearly equal time duration approximating a 50 percent duty cycle. The cyclical waveform has one or more non-linear portions reflected in the content of the read only memory.

Abstract: A self-calibrating video circuit comprises a first and second digital-to-analog converter generating first and second output signals, and a calibration circuit coupled with the first and second digital-to-analog converters for calibrating the first digital-to-analog converter output signal to the output signal of the second digital-to-analog converter.

Abstract: A digital noise-shaping filter with real coefficients for delta-sigma data converters used in a digital amplifier, 1-bit digital/analog converter, 1-bit analog/digital converter and the like, and a method for making the same. The present digital noise-shaping filter has improved noise suppression performance and system stability and reduced calculation complexity. To this end, the digital noise-shaping filter comprises a noise transfer function expressed by NTF(z)=−1+a1z−1+a2z−2+&Lgr;+aNz−N. The noise transfer function has optimum real coefficients or real coefficients approximating them.

Abstract: A planar mode converter includes a rectangular waveguide, a microstrip feed-in circuit, and a microstrip feed-out circuit. The rectangular waveguide is filled with dielectric layers and surrounded with metal materials. The lowermost dielectric layer has usually largest thickness and dielectric constant. Except for the lowermost dielectric layer, each of the dielectric layers has a rectangular aperture at its front-end and back-end, respectively. The microstrip feed-in circuit is constituted by first, second and third metal strips, and a feed-in metal ground plane. The first metal strip and the feed-in metal ground plane form a feed-in signal line. The first, second and third metal strips are adhered to the top surface of the lowermost dielectric layer, and the feed-in metal ground plane is adhered to the bottom surface of the lowermost dielectric layer. The microstrip feed-out circuit is constituted of fourth, fifth and sixth metal strips, and a feed-out metal ground plane.

Abstract: A switched capacitor integrator that shares a switched capacitor CAP1 at the input of the integrator for the signal input and the reference capacitor. The operation of the circuit includes discharging the capacitor CAP1 with a first clock signal CK3; transferring an input voltage IN onto the capacitor CAP1 with a second clock signal CK1′; applying a reference voltage REF to a first end of the capacitor CAP1 with a third clock signal CK2; and coupling a second end of the capacitor CAP1 to the integrator with the third clock signal CK2 while the reference voltage REF is applied to the first end of the capacitor CAP1.

Abstract: A method for selectively and sequentially converting digital video data signals in three formats, namely, standard definition, progressive scan and high definition formats to analogue form such that the same analogue reconstruction filter can be used for filtering the analogue forms of the signals after conversion. The digital signals prior to being converted are over-sampled at respective over-sampling frequencies for displacing image frequencies to frequencies sufficiently spaced apart from the widest band width signal so that the analogue reconstruction filter can be provided for filtering the widest band width signal as well as the other band width signals and also can be provided with a relatively low roll-off rate of attenuation.

Abstract: A machine used for multi-stage analog-to-digital (A/D) conversion accepts as a stage input an unknown analog input signal and produces as a stage output a residue signal which is negatively scaled with respect to the unknown analog input signal. Combination of the unknown analog input signal and adjustment signals and scaling are accomplished using a circuit requiring only a single op-amp and corresponding output settling delay. The negatively scaled residue signal is passed as input to the following stage. The effects of negative scaling are compensated for in the following stage with proper connection of desired pre-generated reference signals to the second stage's comparators. The invention has a much lower implementation cost than full flash A/D conversion, particularly for high-precision conversions. The invention is also faster than successive approximation (SA) A/D conversion. With proper design, the implementation cost of the present invention can be less than that of prior art SA A/D converters.

Abstract: A method and apparatus for achieving relatively low compression ratios based on the realization of using a longer history and longer common strings of the input data stream as an initial evaluation of the input data prior to applying a particular compression process. More particularly, the input data is preprocessed by applying string-matching to the extract long common strings. The input data is divided into a series of blocks with each individual block having a uniform size, illustratively, 1000 characters in length. Further, a so-called fingerprint is computed and stored for each block. Thereafter, the input data stream is traversed and comparison is made between a particular set of character of the input stream and the computed fingerprints. In particular, the input stream is traversed as a function of a sliding window wherein the present window of characters of the input is compared to the computed fingerprints.

Abstract: A method for serializing bits without introducing glitches (i.e., spurious signals) into the serialized data stream is disclosed. Furthermore, the embodiments of the present invention do not require a timing signal (e.g., a clock signal, etc.) at the frequency of the serialized data stream. On the contrary, the illustrative embodiment of the present invention requires timing signals with a frequency equal to the rate at which words are loaded into the serializer. The illustrative embodiment comprises: a first unanimity gate for generating a first binary waveform based on a first coincidence function of a second binary waveform and a third binary waveform; a second umanimity gate for generating a fourth binary waveform based on a second coincidence function of the first binary waveform and a fifth binary waveform; and a first temporal delay device for receiving the fourth binary waveform and for generating the third binary waveform based on the fourth binary waveform.

Abstract: A system and method for the on-demand transcoding of media content from a source type to a destination type is provided, wherein the system includes a plurality of transcoders for transcoding from a plurality of source types to a plurality of destination types, and wherein the system receives a transcoding request for media content, fetches the media content in response to the transcoding request, sends the media content to one of the plurality of transcoders based on the source type and destination type, transcodes the media content from the source type to the destination type, thereby generating transcoded media content, and transmits the transcoded media content. The system fetches, sends, and transcodes the media content and transmits the transcoded media content in a pipelined fashion. The system also provides for the publication of media content as a file or stream of digital data, for the archiving of media content, and the caching of transcoded media content to improve system efficiency.

Abstract: Encoding tables are accorded with variable-length encoding rules using a variable constraint length. A DSV control bit is periodically inserted into a first input bit stream to generate a second input bit stream. Every m-bit piece of the second input bit stream is encoded into an n-bit output signal forming at least a portion of an output code word by referring to the encoding tables. Thereby, the second input bit stream is converted into a first output bit stream composed of output code words and observing RLL (d, k). A sync word is inserted into the first output bit stream for every frame to generate a second output bit stream. A frame-end output code word is terminated at a position before a next-frame sync word. DSV control of the second output bit stream is implemented in response to the inserted DSV control bits.

Abstract: A 6-bit output code word is generated in response to every 4-bit input code word by referring to a set of encoding tables. The encoding tables contain output code words assigned to input code words, and contain encoding-table designation information accompanying each output code word. The encoding-table designation information designates an encoding table among the encoding tables which is used next to generate an output code word immediately following the output code word accompanied with the encoding-table designation information. Two redundant bits are added to every prescribed number of the successive generated output code words for digital-sum-variation control. The generated output code words and the added redundant bits are sequentially connected into a redundant-bit-added output-code-word sequence which follows predetermined run length limiting rules (1, k)RLL, where “k” denotes a predetermined natural number equal to 9.

Abstract: A DAC (1) comprises a pair of outer strings (4,5) of resistors Ra and Rb and an inner string (12) of resistors Rc connected in series with the outer string (4,5). The inner string (12) converts the LSBs, while the outer strings convert the MSBs. Outer switch networks (10,11) of switches Sa and Sb selectively switch the outer strings (4,5) to reference voltage terminals Vref+ and Vref− (8,9) for selectively coupling selected portions of the outer strings (4,5) to the respective voltage reference terminals (8,9) for decrementing the inner string (12) in steps corresponding to one MSB between the terminals (8,9). An inner switch network (15) of switches Sc selectively connects an analog output terminal (2) to one of the resistors Rc; corresponding to the LSBs so that the analog voltage on the output terminal corresponds to the digital input signal.

Abstract: A segmented digital-to-analog converter circuit employs a tri-level technique to provide an output current in response to a bit code. DAC slice circuits are activated in unary fashion in response to their respective control signal, which are provided by a decoder circuit in response to the high-order bits. Each DAC slice circuit provides a binary weighted current to a summing node in response to the middle-order bits. One of the DAC slice circuits is selected to direct a portion of its total current to the input of a DAC_LOW circuit, where the input current is divided to provide a divided current to the summing node in response to the low-order bits. At certain code transitions a different DAC slice circuit is selected to provide the input current, and the previously selected DAC slice circuit redirects its total current to the summing node such that differential non-linearity errors are minimized.

Abstract: A non-uniform analog-to-digital converter (ADC) produces digital output data representing the magnitude of an analog input signal having a non-uniform magnitude probability distribution. The digital output data represents the analog input signal with relatively high resolution for the input signal's more frequently occurring magnitudes and with relatively lower resolution for the input signals less frequently occurring magnitudes.