Abstract: A memory system (3) for storing data messages communicated between a processor unit (13) and a communication module (11), each data message comprising at least one data word, comprises a memory array (4) having a plurality of memory buffers (B0-BM), each buffer for storing a data message, and logic circuitry (24) coupled to the memory array (4). The logic circuitry (24) sets one bit of a data message stored in a memory buffer to a first logic state during a processor unit read access when the processor unit (13) reads a current data message from the memory buffer, and negates the one bit to a second logic state during a communication module write access when the communication module (11) writes a new data message into the memory buffer.

Abstract: A recording and/or reproducing system has a recording and/or reproducing section and an interfacing unit. The recording and/or reproducing section records and/or reproduces digital data or digital signals on or from a loaded recording medium, such as a magnetic tape. The interfacing unit has a first input/output section for exchanging data and/or signals with an external equipment and a second input/output section for exchanging data and/or signals with the recording and/or reproducing section.

Abstract: A queuing architecture within a RAID controller that manages a multi-threaded SCSI environment. The architecture resides within a RAID controller that communicates with a plurality of independent, SCSI disk drives (or other storage elements). The RAID controller accepts disk I/O requests from one or more host computers. The architecture dynamically allocates multiple disk I/O requests to various request queues until the disk drive that will handle the request is available for access. Multiple requests are executed in parallel on various ones of the disk drives.

Abstract: An apparatus and method are described for supporting a plurality of connections between a client computer and a network server. The client computer supports a plurality of simultaneously logged on ("active") services. The client computer creates a connection for each set of distinct credentials supplied by services logged onto the client computer. The client computer includes a redirector for maintaining independent control, status and data information for a plurality of independent connections associated with the plurality of simultaneously active services having distinct sets of credentials.

Abstract: A method and system is provided for assigning addresses to input/output (I/O) devices in a control network, and for verifying addresses assigned to the I/O devices. The system comprises a logic controller providing memory into which a connectivity map may be programmed. The connectivity map defines a specific expected address for each I/O device in the system. The logic controller further provides an external controller bus and logic for downloading the connectivity map to an I/O bus manager connected to the logic controller via the external controller bus. The I/O bus manager provides logic for assigning the specific addresses to the I/O devices. Network nodes connect the I/O bus manager to I/O cluster units in the system, each network node including a multiplexer for multiplexing output signals from the I/O bus manager and a demultiplexer for demultiplexing input signals from the I/O cluster units, the multiplexing/demultiplexing functions provided by a controller area network (CAN) integrated circuit.

Abstract: The present invention is directed to a display FIFO module for use in DRAM interface that includes a DRAM controller sequencer which prioritizes requests for DRAM access received from various modules, such as a CPU, a blit engine module, and a half frame buffer logic module, etc. The display FIFO module is connected between the DRAM controller sequencer and a display pipeline which is connected to a display device. The display FIFO module issues low and high priority requests for DRAM access to the DRAM controller sequencer for loading the FIFO with display data to be transferred to the display device. The low priority request is issued at the earliest time when the display FIFO is capable of accepting new data without overwriting unread data. This is determined by comparing the FIFO data level against a predetermined low threshold value. The low priority request is issued when the FIFO data level falls below or is equal to the low threshold value.

Abstract: A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. The host bridge includes an outbound data path, an inbound data path, and a control mechanism.

Abstract: A portable information storage and transfer device for use with IC memory card-based portable computers obviates many operations traditionally requiring a desktop computer. The floppy disk drive in the information storage and transfer device allows large amount of data and software programs to be made available to the IC memory card-based computer on floppy disks. The contents of such floppy disk can then be transferred for use in the portable computer on a blank IC memory card or the portable computer's system memory. Information entered into and stored in the system memory or an IC memory card of the portable computer can also be transferred through the information storage and transfer device to floppy disks, to a printer, to various peripheral devices or to a host computer. A built-in modem for accessing facsimile machines, other modems and the telephone system is also provided.

Abstract: An information verifying apparatus for verifying information recorded on a recording medium. One unit of information input is recorded on a storage medium and is retrieved from the storage medium. A buffer memory stores the one unit of information input, the one unit of information stored in the buffer memory being the same as the one unit of information recorded on the storage medium. An output controller outputs the retrieved information and controls the timing of output of the retrieved information. A comparator compares the information from the buffer memory with the information from the output controller. Since the information is verified using a buffer memory and on output controller, verification can be quickly performed without the use of a large quantity of memory.

Abstract: A channel time-out apparatus in a data processing system having a channel processor for controlling the allocation of a plurality of input/output channels. The channel time-out apparatus comprises a clock for generating time indications, an address generator for generating an address for each input/output channel of the plurality of input/output channels, a time-out generator for generating a time-out indicator for an input/output channel whenever that input/output channel processes an instruction, storage for storing the last time-out indicator generated by the time-out means for each input/output channel and a comparator for comparing the last time-out indicator stored in the storage for the input/output channel whose address is presently being generated by the address generator with a time indicator presently being generated by the clock for determining when a time-out event has occurred without requiring intervention by the processor.

Abstract: A method in which access control programs (ACPs) permit controlled delegation of access rights from clients to untrusted intermediaries. ACPs are programs that encode arbitrary specifications of delegated access rights. In the method, a client creates an ACP and associates it with a request to a server, the request being made through one or more intermediaries. When processing a request received from an intermediary, the server executes the access control program to determine whether or not to grant the request.

Abstract: A hotel room entertainment system enables video games to be played in each room of a hotel without providing a video game generator in each room. The entertainment system includes at a head end system portion in which the video game audio and video signals are generated and a plurality of guest terminals. Game interrogations are provided to each guest terminal in an active game-playing mode, each game interrogation having a plurality of response positions for guest terminal responses to the interrogation. The game interrogations are interleaved with a series of system interrogations generated at the head end system, enabling the entertainment system to provide video game signals along with other entertainment and services to the guest terminals using a single distribution system.

Abstract: An information handling system includes one or more processors, a system bus or network connecting the processors, a memory system connected to the system bus, an asynchronous signal controller connected to the system bus, one or more I/O bridges connected to the system bus, an I/O bus connected to each I/O bridge, one or more devices connected to the I/O bus, including perhaps another I/O-bus-to-I/O-bus bridge where additional devices may be connected to a second I/O bus, wherein the first or host bridge includes remote interrupt control logic having a register wherein an input to each position in the register is from one of the I/O devices downstream from the host bridge, and a shadow register address buffer, both under the control of a sample circuit connected to outputs of the register such that when a change in any register position is detected by the sample circuit, the entire contents of the register are sent to the shadow register indicated in the shadow register address buffer by a processor bypass t

Abstract: At least two circuit elements are interconnected by a bus which permits transmission of information between the circuit elements. A clock signal generator generates a clock signal alternately of at least two frequencies, namely, a low frequency and a high frequency. When information is not transmitted upon the bus, the clock signal generator generates the clock signal of the low frequency, and the circuit is operated at the low frequency level. When information is generated upon the bus, the clock signal generator generates a clock signal of the high frequency and the circuit is operated at the high frequency. Detection of a start bit, for example, forming a first bit of a word transmitted upon the bus, once detected, causes the clock signal generator to generate the clock signal of the increased frequency.

Abstract: An interface controller for an addressable interface module. The interface module is for coupling along with other addressable interface modules over a communication bus to a central processor. Each interface module responds to a unique base address, unique to such interface module provided by the central processor on the communication bus, responsive either to a read command for reading data from such interface module to the communication bus or to a write command for writing data from the communication bus to such interface module. A stored configuration base address is provided in the interface controller for use in determining the unique address for which the corresponding interface module is to respond. A decoder in the interface controller decodes the base address including a modified configuration address for use by the corresponding interface module in determining the unique address for response by the corresponding interface module.

Abstract: A system for linking a first computer to a second computer is disclosed. The system of the present invention comprises a network. A first computer is coupled to the network. A second computer is coupled to the network. A server is coupled to the network for receiving a request for direct linking from the first computer and a request for direct linking from the second computer, matching the first computer with the second computer using matching criteria received from the first computer and the second computer, and sending a network address of the second computer to the first computer. The first computer further comprises a circuit for establishing a communication link with the second computer.

Abstract: A diffracting token router for executing a correctness invariant. The diffracting token router is connected to at least one producer of tokens and at least two consumers of tokens. The diffracting token router includes an array of inlet wires, an array of outlet wires, a diffracting prism connected to the array of inlet wires and the array of two outlet wires and a decision decider connected to the diffracting prism and the at least two outlet wires. The diffracting taken router has two operative modes. In its first operative mode, two or more tokens arrive at the diffracting prism in a diffracting collision manner according to the correctness invariant, and are thereafter routed to the array of output wires according to the correctness invariant.

Abstract: An interrupt request processing device and method for control of the bus cycle of a microprocessor which implements predetermined wait periods dependent upon a detected wait request. Predetermined wait states, programmable in the microprocessor, are assigned to wait request signals for implementation of a predetermined wait period corresponding to a detected wait request signal, in which the bus cycle is suspended for the predetermined wait period while the signal to be applied to the connected peripheral device is held during access to the peripheral device. After the predetermined wait period is over the bus cycle is unsuspended and the microprocessor is again able to detect wait request signals.

Abstract: A method in accordance with the invention is implemented via a set of novel computer programs referred to for convenience as NEWPROG. A "controller NEWPROG," resides in one or more communication controllers on an SNA network as a "front end" processor for the NCP executing in that controller. The controller NEWPROG uses interception techniques to monitor the controller's incoming and outgoing messages and thereby 1) collect statistical information about network performance, and 2) exchange "backchannel" messages with controller NEWPROGs operating in adjacent controllers. The controller NEWPROG can alter dynamically the tuning parameters in that NCP. A "host NEWPROG" executes in a host computer to provide a monitoring and control station for a network administrator. The host NEWPROG communicates with controller NEWPROGs on the network via a virtual logical unit (VLU) executing within at least one controller.

Abstract: A stealth interface for an intelligent front-end communication system couples a plurality of actively redundant process control computers to a computer network. The stealth interface in each of the actively redundant process control computers includes a multi-ported memory for storing dynamic data associated with the physical process and for transferring this data to a front end computer which is in communication with the computer network. The multi-ported memory also includes a mailbox section for storing messages sent between the front end computer and its actively redundant process control computer. The stealth interface also includes a guardian circuit which ultimately controls the ability of the front end computer to write information to specific memory locations in the multi-ported data memory.