Patents Examined by Larry T Mackall
  • Patent number: 11567698
    Abstract: A storage device is configured to manage a plurality of nonvolatile memories with a plurality of physical streams. An operation method of the storage device includes receiving an input/output request from an external host device, determining a 0-th virtual stream identifier, extracting a 0-th representative value from a 0-th virtual stream feature, extracting a first and second representative values corresponding to first and second physical streams, calculating distance information including first and second similarities between the 0-th virtual stream and each of the first and second physical streams, based on the extracted representative values, assigning one of the plurality of physical streams to the 0-th virtual stream, based on the distance information, and performing an operation corresponding to the input/output request, at the assigned physical stream, and the extracting and the calculating are performed by using machine learning model.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: January 31, 2023
    Inventors: Jungmin Seo, Byeonghui Kim, Kibeen Jung, Seungjun Yang
  • Patent number: 11561695
    Abstract: In a storage system such as a SAN, NAS, or storage array that implements hierarchical performance tiers based rated drive access latency, on-drive compression is used on data stored on a first tier and off-drive compression is used on data stored on a second tier. Off-drive compression is more processor intensive and may introduce some data access latency but reduces storage requirements. On-drive compression is performed at or near line speed but generally yields lower size reduction ratios than off-drive compression. On-drive compression may be implemented at a higher performance tier whereas off-drive compression may be implemented at a lower performance tier. Further, space saving realized from on-drive compression may be applied to over-provisioning.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: January 24, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventor: James M Guyer
  • Patent number: 11550506
    Abstract: A method for processing requests, that includes receiving, by a volatile storage component, a request from a user space application, writing the request into a shared memory partition, generating instructions associated with the request, and processing the instructions, where the request is a data request and where generating the instructions associated with the request includes detecting, by the volatile storage component, the data request in the shared memory partition, where the data request is written in a data queue.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: January 10, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Rajeev Tiwari, Yong Zou
  • Patent number: 11544006
    Abstract: A storage device may include a non-volatile memory including a plurality of zones, the non-volatile memory configured to sequentially store data in at least one of the plurality of zones, and a processing circuitry configured to, receive a first write command and first data from a host, the first write command including a first logical address, identify a first zone of the plurality of zones based on the first logical address, compress the first data based on compression settings corresponding to the first zone, and write the compressed first data to the first zone.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: January 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongik Jeon, Kyungbo Yang, Seokwon Ahn, Hyeonwu Kim
  • Patent number: 11543985
    Abstract: Techniques for management of data storage in distributed storage systems are provided. A method may include receiving, by a computer system, a request to write data to a volume. The method may include identifying, by the computer system, a zone segment mapped to the volume. The zone segment may include a plurality of zones. The method may include identifying, by the computer system, a segment pointer indicating a write location in a zone of the zone segment. The method may include writing, by the computer system, the data to one or more zones of the plurality of zones of the zone segment, starting at the write location. The method may also include updating, by the computer system, the segment pointer according to a data endpoint of the data in the zone segment.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: January 3, 2023
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Erich Stephen Otto, Michael Warren Kirby, Ajinkya Pramod Kulkarni
  • Patent number: 11537327
    Abstract: Devices and techniques for an adjustable watchdog in a memory device are disclosed herein. A memory operation command is received at a first time with a memory device from a host. A reset signal is received, with the memory device from the host, at a second time following the first time. A time interval between the first time and the second time is measured. A delay interval for a timer in the memory device to reset the memory device independently of receiving a further reset signal from the host is established based on the measured time interval.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nadav Grosz, David Aaron Palmer
  • Patent number: 11537321
    Abstract: Systems, apparatuses, and methods related to media type selection are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile) and can write data to the memory media types. Data inputs can be written (e.g., stored) in a particular type of memory media based on characteristics (e.g., source, attributes, and/or information etc. included in the data). For instance, selection of a portion of data can be based on the quality of the data received. In an example, a method can include receiving, by a memory system of a mobile device that comprises a plurality of memory media types, data from the assigned image sensor of a plurality of image sensors of the mobile device; and selecting a portion of data from the received data based on one or more characteristics of the data that indicate a quality of an image or images represented by the portion of data.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bhumika Chhabra, Carla L. Christensen, Zahra Hosseinimakarem
  • Patent number: 11531624
    Abstract: Apparatus for data processing and a method of data processing are provided. Address translation storage stores address translations between first set addresses and second set addresses, and responds to a request comprising a first set address to return a response comprising a second set address if the required address translation is currently stored therein. If it is not the request is forwarded towards memory in a memory hierarchy. A pending request storage stores entries for received requests and in response to reception of the request, if a stored entry for a previous request indicates that the previous request has been forwarded towards the memory and an expected response to the previous request will provide the address translation, intercepts the request to delay its reception by the address translation storage. Bandwidth pressure on the address translation storage is thus relieved.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: December 20, 2022
    Assignee: Arm Limited
    Inventors: Viswanath Chakrala, Andrew Brookfield Swaine
  • Patent number: 11531494
    Abstract: Provided herein may be a storage device configured to check a status of a memory device based on data read without output of a status check command, and determine a subsequent command to be generated. The storage device may include a memory device and a memory controller configured to control the memory device. The memory device may include a read data generator configured to generate new read data including both read data corresponding to a read command received from the memory controller and information indicating a status of the memory device. The memory controller may include: a status information determiner configured to determine the status of the memory device based on the new read data received from the read data generator and generate status information and a command generator configured to generate a command to be output to the memory device based on the status information.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: December 20, 2022
    Assignee: SK hynix Inc.
    Inventor: Dong Jae Shin
  • Patent number: 11531615
    Abstract: A controller controls an operation of a semiconductor memory device. The controller includes a request analyzer, a storage, and a garbage collection controller. The request analyzer generates invalid data information, based on an erase request received from a host. The storage stores a garbage collection reference table representing memory blocks excluded from selection as a victim block on which a garbage collection operation is to be performed, based on the invalid data information. The garbage collection controller controls the garbage collection operation on the semiconductor memory device, based on exclusion block information generated according to the garbage collection reference table.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: December 20, 2022
    Assignee: SK hynix Inc.
    Inventors: Se Hyun Kim, Hui Jae Yu
  • Patent number: 11520486
    Abstract: A backup data storage system includes non-volatile memory units, a disk interface coupled to at least some of the non-volatile memory units, a connection component that facilitates exchanging data with the backup data storage system, and a smart network interface controller, coupled to the disk interface and the connection component to provide tape emulation to a host coupled to the backup data storage system. The disk interface, the connection component, and the smart network interface controller may be coupled using a PCIe bus. Tape data written to the backup storage device may be stored on the non-volatile memory units. A processor coupled to the smart network interface controller and the disk interface may receive the data from the smart network interface controller and may provide the data to the disk interface to store the data on the non-volatile memory units. The connection component may be a FICON connection component.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: December 6, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Adnan Sahin, Douglas E. LeCrone, Ian Wigmore
  • Patent number: 11507320
    Abstract: A USB-based cloud disk according to an embodiment is connected with a computer, and, when a write command on a sector is received from the computer, the USB-based cloud disk transmits data regarding the sector and a data path regarding the sector data to a remote repository.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: November 22, 2022
    Assignees: OPENBOXLAB INC.
    Inventor: Chong Ho Kim
  • Patent number: 11507311
    Abstract: A storage device including a nonvolatile memory device is described. The storage device includes a controller that receives a write command and data from an external host device. The controller preferentially writes the data in an area based on a normal write policy when the data is associated with a normal write, and in an area based on a turbo write policy when the data is associated with a turbo write. The controller may also receive a read command, to read data from an area based on the read command, and output the data to the external host device. The controller may also move the data in response to move information of the read command when the read command is received together with move information.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: November 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Woo Park, Dong-Min Kim
  • Patent number: 11507318
    Abstract: Disclosed is a storage device, which include a non-volatile memory device including a plurality of memory blocks, a buffer memory, and a storage controller that receives a first allocation request and first logical address information from a host, allocates logical addresses of the first logical address information to a first physical group of the plurality of memory blocks in response to the first allocation request, receives a first write request and first write data associated with the first logical address information, stores the first write data in the buffer memory, and writes the first write data stored in the buffer memory in memory blocks of the first physical group in response to the first write request. The first allocation request precedes the first write request.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: November 22, 2022
    Assignee: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Sang-Won Lee, Gihwan Oh, Soyee Choi, Jonghyeok Park
  • Patent number: 11507273
    Abstract: A method of data reduction in a block-based data storage system includes selecting a starting position in a block based on a deterministic function of block data content. Then for an unaligned block beginning at the selected starting position, a block digest (e.g., block hash) is generated and compared with stored block digests of stored data blocks. If there is a match, and the stored block matches the unaligned block, then a reference to the stored block is stored in place of the unaligned block, and otherwise the unaligned block and a corresponding digest are stored. The storing of references to already stored blocks, without the constraint of observing aligned-block boundaries, realizes increased savings of physical storage space.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Uri Shabi, Ronen Gazit
  • Patent number: 11500564
    Abstract: A block family associated with a memory device is initialized. An initial value of a power cycle count associated with the memory device is stored. Responsive to programming a block residing in the memory device, the block is associated with the block family. Responsive to determining that a current value of the power cycle count exceeds the initial value of the power cycle count, the block family is closed. Responsive to determining that a time period that has elapsed since initializing the block family exceeds a threshold period, the block family is closed.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: November 15, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Peter Feeley, Karl D. Schuh
  • Patent number: 11494077
    Abstract: A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: November 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Yasushi Nagadomi
  • Patent number: 11487437
    Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: November 1, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yun-Tzuo Lai, Haining Liu, Subhash Balakrishna Pillai
  • Patent number: 11481152
    Abstract: A controller of a memory sub-system can, responsive to providing a command completion signal to a host, mark a portion of a plurality of commands that are addressed to a same logical block of the memory devices, reorder the marked portion of the plurality of commands, wherein write commands from the marked portion of the plurality of commands are given priority over read commands from the marked portion of the plurality of commands, execute a newest write command from the marked portion of the plurality of commands prior to executing read commands, addressed to the same logical block, from the marked portion of the plurality of commands, and execute read commands from the marked portion of the plurality of commands in on an order in which the read commands were received and after the execution of the newest write command, wherein the read commands are executed responsive to an execution of the newest write command.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: October 25, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Venkat R. Gaddam
  • Patent number: 11474939
    Abstract: The present technology relates to a memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells, a data register connected to the memory cell array through a bit line and configured to store data sensed through the bit line, a cache register configured to cache the data stored in the data register, and a control logic configured to control a caching operation of receiving a cache read command from a memory controller and storing the data, which is stored in the data register, in the cache register, during a cache read period, in response to the cache read command, wherein the control logic controls the caching operation based on whether the cache read command is a first command received after receiving a normal read command from the memory controller.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: October 18, 2022
    Assignee: SK hynix Inc.
    Inventor: Yong Soon Park