Patents Examined by Laura Thomas
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Patent number: 5644475Abstract: A solder resist pattern for a single in-line package (SIP) finger connector, or other interface member includes small solder resist features spaced closely together. The features can be circular, square, diamond-shaped, star-shaped, or other geometry and preferably are placed on finger connectors in a photo-imaging process. The pattern includes meniscus channels which are narrow enough to prevent solder from adhering to the finger connectors. The surface area of the features is small enough so that the pattern can be easily removed by a low impact or non-contact operation. Preferably, the pattern is removed by a hot air solder knife after the board is subjected to a solder wave.Type: GrantFiled: April 11, 1995Date of Patent: July 1, 1997Assignee: Allen-Bradley Company, Inc.Inventors: Gerard A. Woychik, John C. Mather
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Patent number: 5644476Abstract: The invention relates to a method of manufacturing a flexible fastening member (19) comprising a foil (1) for fastening an object (15) thereto, characterized by making at least two generally U-shaped incisions (5) which are spaced apart, which define a central portion (23) between them, and which are directed oppositely to another, the open ends of the U-shapes facing away from another so as to create two mutually opposed tags (11), and by bending the foil (1) along two parallel bending lines (13), each line being situated at the open end of a U-shaped incision (5) so as to obtain a generally U-shaped member (19) whose base is said central portion (23), and to obtain the tags (11) as extensions of the legs (25) of said U-shaped member and situated at one side of the plane (20) defined by the central portion (23), the legs (25) being situated at the other side of said plane (20).Type: GrantFiled: October 13, 1994Date of Patent: July 1, 1997Assignee: U.S. Philips CorporationInventors: Johannus W. Weekamp, Johannes Brandsma
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Patent number: 5641945Abstract: A contacting structure with respect to a spherical bump in which the spherical bump is to be contacted with a contact pin, the contact pin includes a contacting portion supported by a resilient support element, and the contacting portion is arranged in opposite relation to that part of a spherical surface of the spherical bump other than a lower-most point thereof. The contacting portion has a projection capable of pressing into the spherical surface of the spherical bump, and also has a pressure receiving surface for setting an amount by which the projection presses into the spherical surface.Type: GrantFiled: September 7, 1995Date of Patent: June 24, 1997Assignee: Yamaichi Electronics Co., Ltd.Inventors: Shunji Abe, Kazumi Uratsuji
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Patent number: 5641944Abstract: A multilayer circuit board or laminated circuit board for use in a motor controller is described. The multilayer circuit board is preferably utilized as a power substrate module. The power substrate module includes a mounting area provided in a recess, window or portion of the circuit board where the circuit board is only a single layer thick. The insulated mounting area is provided in a blind via in the multilayer circuit board. The single circuit board layer at the mounting area provides a heat conductive yet highly electrically insulated mounting area for receiving a heat sink. The heat sink can be mounted on a side opposite the electrical device. The heat sink may be standard heat sink or a copper coil directly soldered to the circuit board. The multilayer circuit board includes an enhanced conductive layer for receiving the surface mount device. The enhanced conductive layer preferably includes an insulative frame which holds copper slugs.Type: GrantFiled: September 29, 1995Date of Patent: June 24, 1997Assignee: Allen-Bradley Company, Inc.Inventors: Christopher J. Wieloch, Thomas E. Babinski, John C. Mather
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Patent number: 5641946Abstract: Method and circuit board structure for leveling the tops of solder balls of a BGA semiconductor package is disclosed. In order to level the solder balls, the sizes of solder ball lands used for welding the solder balls to the circuit board are controlled in accordance with portions of the circuit board. The invention thus achieves the coplanarity of the solder balls regardless of thermal bending of the plastic body and circuit board of the BGA semiconductor package. In an embodiment, a plurality of solder ball lands having different sizes are formed on the circuit board prior to forming the solder balls on the lands. In another embodiment, a plurality of solder ball lands having the same size are formed on the circuit board prior to forming an insulating mask on the circuit board in order to form differently-sized exposed inside portions of solder ball lands.Type: GrantFiled: January 18, 1996Date of Patent: June 24, 1997Assignees: Anam Industrial Co., Ltd., Amkor Electronics, Inc.Inventor: Il Kwon Shim
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Patent number: 5639994Abstract: A bypass piece is formed at a forward end of a extension part. Three bypass Cu wiring patterns, which cannot be formed at a extension part, are formed at the bypass piece. The bypass piece is bent from the forward end of the extension part towards the main body so as to overlap the extension part. Connecting portions of the bypass Cu wiring patterns of the bypass piece are soldered to end portions of wiring patterns of the main body.Type: GrantFiled: November 22, 1995Date of Patent: June 17, 1997Assignee: Fuji Photo Optical Co., Ltd.Inventor: Kazuhisa Tanaka
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Patent number: 5639989Abstract: Electronic components are shielded from electromagnetic interference (EMI) by one or more conformal layers filled with selected filler particulars for attenuate specific EMI frequencies or a general range of frequencies. Shielding is accomplished through the use of a single general purpose shielding layer, or through a series of shielding layers for protecting more specific EMI frequencies. In a multilayer embodiment, a semiconductor device (50) is mounted on a printed circuit board substrate (16) as a portion of an electronic component assembly (10). A conformal insulating coating (24) is applied over the device to provide electrical insulation of signal paths (e.g. leads 54 and conductive traces 18) from subsequently deposited conductive shielding layers. One or more shielding layers (60, 62, and 64) are deposited, and are in electrical contact with a ground ring (56).Type: GrantFiled: April 19, 1994Date of Patent: June 17, 1997Assignee: Motorola Inc.Inventor: Leo M. Higgins, III
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Patent number: 5637832Abstract: A method for manufacturing an electronic module comprising a substrate carrying circuitry and one or more integrated circuits and having an array of closely spaced solder balls electrically connected with terminals of the circuitry to connect the module to an array of terminals, as on printed circuit board. The array of solder balls is fabricated on the substrate by preparing the substrate to include an array of terminal pads, perforating a sheet of dielectric tape to create precise and uniform holes, and thereafter fusing the tape onto the substrate so that the holes are aligned over the substrate's terminal pads. Solder balls are then placed in the holes and heated to reflow them, so that part of the solder fills a volume defined by the holes in the dielectric tape and bonds to the terminal pads on the substrate, while the solder balls remain generally spherical above the dielectric tape.Type: GrantFiled: January 11, 1996Date of Patent: June 10, 1997Assignee: Pacific Microelectronics CorporationInventor: Paul A. Danner
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Patent number: 5637833Abstract: Solder is applied to a circuit board 7 by dipping the board into a bath 1 of molten solder 3, the molten solder having a layer of oil 5 on top. The solder is dipped into the bath by rotating it along a path that is substantially coplanar with the circuit board. This is achieved by supporting the board on a carrier 9 which in turn is attached to a motor shaft 11.Type: GrantFiled: June 5, 1995Date of Patent: June 10, 1997Assignee: International Business Machines CorporationInventors: Peter M. Banks, William M. Morgan
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Patent number: 5637834Abstract: A multi-layer circuit substrate (500 ) includes at least two substrate layers (130, 150). The first substrate layer (130) has an insulating material (100) with two opposing surfaces (101, 102), and a hole (105) extending between the two surfaces (101, 102). A conductive pattern (110) is formed on a first surface (101) of the insulating material (100) and completely covers the hole (105). The second substrate layer (150) is attached along the second surface (102) of the insulating material (100), and also includes a conductive pattern (155) on insulating material. A conductive material (140) is disposed within the hole (105) that engages the first and second conductive patterns (110, 155).Type: GrantFiled: February 3, 1995Date of Patent: June 10, 1997Assignee: Motorola, Inc.Inventors: Frank J. La Bate, Jr., John A. De Santis, Anthony B. Suppelsa, Sr.
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Patent number: 5637835Abstract: A method and apparatus providing an automated means for detecting unsoldered thru-hole connector leads is herein disclosed. This means consists of a thru-hole connection pad and a test pad positioned in close proximity to each lead of an electrical component. A thru-hole connection pad is formed about the periphery of each thru-hole. It serves to form a solder pad for securing the lead to the printed circuit board and establishes an electrical connection between the component and reverse sides of the printed circuit board. A test etch easily accessible by an automated testing device is positioned within close proximity of each thru-hole connection pad. As each lead is individually soldered to the printed circuit board, a solder bridge must also be formed across the thru-hole connection pad and the test etch thereby establishing an electrical connection between the lead and the test etch. This electrical connection is used by an automated testing device to detect any unsoldered leads.Type: GrantFiled: May 26, 1995Date of Patent: June 10, 1997Assignee: The Foxboro CompanyInventor: Michael L. Matern
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Patent number: 5633480Abstract: Conductive circuits (copper foil) are provided on both surfaces of a basefilm. A first prepreg is laminated onto both surfaces of the basefilm. A cover lay is provided at an opening portion of the basefilm. The cover lay may extend to a through-hole. The semirigid cover lay, made from polyimide-containing resin material, is placed to cover the opening portion, thermocompressed, and bonded to be laminated onto the surface of the basefilm. A second prepreg having an opening portion whose shape is substantially similar to the opening portion of the first prepreg, is laminated on the first prepreg.Type: GrantFiled: October 4, 1995Date of Patent: May 27, 1997Assignee: CMK CorporationInventors: Hiromoto Sato, Junzaburo Shirai
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Patent number: 5633479Abstract: Signal wiring layers are formed between a power supply layer and a ground layer, which have conductor patterns each constituted by a plurality of parallel strip-shaped conductors. The above layers are isolated from each other by insulating layers. The signal wiring layer has wires which are arranged in parallel with the parallel strip-shaped conductors of the conductor pattern of the power supply layer, and the signal wiring layer has wires which are arranged in parallel with the parallel strip-shaped conductors of the conductor pattern of the ground layer.Type: GrantFiled: July 25, 1995Date of Patent: May 27, 1997Assignee: Kabushiki Kaisha ToshibaInventor: Naohiko Hirano
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Patent number: 5631446Abstract: An RF flexible printed wiring board transmission line for connecting strip transmission line microwave assemblies without the use of coaxial connectors and coaxial cables. The flexible transmission line includes a thin flexible dielectric ribbon, having on one side a ground plane layer and on the other side a microstrip conductor strip. Plated through holes at the ends of the flexible line provide access to both the ground plane and conductor strip on the same side of the flexible line, to facilitate interconnection of the microwave assemblies to the flexible line. The flexible line operates at microwave frequencies with little or no radiation leakage.Type: GrantFiled: June 7, 1995Date of Patent: May 20, 1997Assignee: Hughes ElectronicsInventor: Clifton Quan
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Patent number: 5631447Abstract: Polymer (preferably polyimide) sheets (10) with laser ablated through-holes plated with metal (20) are used for making electrical conections to specified microcircuits, especially unbumped microchips and Tape Automated Bonding (TAB) articles. Bonding with different melting point materials at opposite ends of the plated holes is disclosed. Preferred polyimides are those derived from polymerisation of 4,4'-biphenyldianhydride and (4,4'-diaminobiphenyl, or 4,4'-diaminobiphenylether, or phylenediamine, preferably p-phenylenediamine).Type: GrantFiled: January 3, 1995Date of Patent: May 20, 1997Assignee: Raychem LimitedInventors: Nicholas J. G. Smith, Michael J. Ludden, Peter Nyholm, Paul J. Gibney
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Patent number: 5629837Abstract: A button contact and array of button contacts are provided for surface mounting a leadless IC device to a circuit board. The button contacts of the button contact array have a substantially flat body lying in a plane and oppositedly directed contact points protruding from resiliently deflectable contact support arms of said body. The button contacts of the invention, which provide a low profile contact between surface mounted components, are suitable for high frequency applications, and particularly high frequency test and burn-in applications, and are relatively durable.Type: GrantFiled: September 20, 1995Date of Patent: May 13, 1997Assignee: Oz Technologies, Inc.Inventors: Nasser Barabi, Iraj Barabi
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Patent number: 5629497Abstract: A prepreg having an opening portion is placed on a cover lay which covers conductive circuits formed on a basefilm. A copper foil sheet is placed on the prepreg in such a way that the copper foil sheet covers the opening portion. The copper foil sheet has no opening portion. Next, the basefilm, the prepreg, and the copper foil are thermocompressed to become one laminate. After making a hole in the laminate, the laminate is plated, and then a through-hole is formed. A conductive circuit is formed by etching the copper foil sheet.Type: GrantFiled: October 4, 1995Date of Patent: May 13, 1997Assignee: CMK CorporationInventors: Hiromoto Sato, Junzaburo Shirai
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Patent number: 5627344Abstract: A multilayer ceramic circuit substrate having therein internal conductor patterns comprising W and/or Mo as a main component and surface conductor patterns comprising Cu as a main component formed onto a surface layer of the multilayer ceramic circuit substrate, wherein an intermediate metal layer comprising 40 to 90 wt. % of W and/or Mo and 10 to 60 wt. % of at least one element selected from the group consisting of Ir, Pt, Ti, and Cr is formed in through-holes of the surface layer and on parts of the surface layer in the vicinity of the through holes on the surface layer, whereby the internal conductor patterns and the surface conductor patterns are electrically connected through the intermediate metal layer. The alumina multilayer ceramic circuit substrate provides an excellent bonding strength and electrical conductivity between the internal conductors and the surface conductors and enables high precision wiring and miniaturization of an electronic circuit part.Type: GrantFiled: December 22, 1994Date of Patent: May 6, 1997Assignees: Sumitomo Metal Ceramics Inc., Nippondenso Co., Ltd.Inventors: Nozomi Tanifuji, Akihiko Naito, Koji Sawada, Tohru Nomura, Yoshiyuki Miyase, Takashi Nagasaka
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Patent number: 5627345Abstract: A multilevel interconnect structure for use in a semiconductor device includes a lower metal wiring having an aluminum or aluminum alloy film and a high melting point metal or high melting point metal alloy film. An interlayer insulating film is deposited on the lower metal wiring and a via hole is formed in the interlayer insulating film. A plug made of aluminum or aluminum alloy is formed in the via hole. An upper metal wiring has an aluminum or aluminum alloy film and a high melting point metal or high melting point metal alloy film. The plug directly contacts the aluminum or aluminum alloy film of at least one of the lower and upper metal wirings to decrease the via resistance without reducing the electromigration reliability.Type: GrantFiled: February 18, 1994Date of Patent: May 6, 1997Assignee: Kawasaki Steel CorporationInventors: Hiroshi Yamamoto, Tomohiro Ohta, Nobuyuki Takeyasu
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Patent number: 5625169Abstract: An electronic part is formed with two dielectric substrates joined together in a face-to-face relationship. Each substrate has an electrode pattern formed on one surface and a grounding surface on the opposite surface. The surfaces with the electrode patterns formed thereon are joined together such that the patterns match each other and are connected to each other. Corners of one of the substrates may be cut so as to expose portions of the electrode pattern on the other substrate. Indentations may be formed on corners and edges of the joined substrates and terminal electrodes and grounding electrodes may be formed in the indentations.Type: GrantFiled: May 22, 1995Date of Patent: April 29, 1997Assignee: Murata Manufacturing Co., Ltd.Inventor: Hiroaki Tanaka