Abstract: A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.

Abstract: A power semiconductor module arrangement includes: a substrate arranged within a housing; at least one semiconductor body arranged on a top surface of the substrate; and a first layer arranged on a first surface within the housing. The first layer includes inorganic filler which is impermeable to corrosive gases and a casting material which fills spaces present in the inorganic filler.

Abstract: In one example, an electronic device includes a substrate having a conductive structure. The conductive structure includes a substrate inward terminal at a first side of the substrate and a substrate outward terminal at a second side of the substrate. The substrate includes a dielectric structure with a first opening is at the second side. An electronic component is at the first side of the substrate and is electrically coupled to the substrate inward terminal, and an encapsulant encapsulates the electronic component. The substrate outward terminal comprises one of a multi-via terminal or a multi-stage via. The multi-via terminal includes pad conductive vias in the first opening a pad dielectric via interposed between the pad conductive vias in the first opening and a conductor comprising a conductor top side with micro dimples over the pad conductive vias and the pad dielectric via.

Abstract: A first lead wiring line and a second lead wiring line intersecting a bending portion of a frame region overlap each other and are electrically connected to each other, and in a first resin layer interposed between the first lead wiring line and the second lead wiring line, a plurality of tapered holes are formed and overlap the first lead wiring line and the second lead wiring line.

Abstract: An image sensor device is provided. The image sensor device includes a substrate having a front surface, a back surface, and a light-sensing region. The image sensor device includes a first isolation structure extending from the front surface into the substrate. The first isolation structure surrounds a first portion of the light-sensing region, and the first isolation structure has a first end portion in the substrate. The image sensor device includes a second isolation structure extending from the back surface into the substrate. The second isolation structure surrounds a second portion of the light-sensing region, the second isolation structure has a second end portion in the substrate, and the second end portion of the second isolation structure is closer to the front surface of the substrate than the first end portion of the first isolation structure.

Abstract: A method of manufacturing the semiconductor structure includes: providing a substrate; forming a first conductive via and a second conductive via extending in the substrate; depositing a first dielectric layer over the substrate and the first and second conductive vias; receiving a waveguide; moving the waveguide to a location over the first dielectric layer and aligning the waveguide with a position of the first dielectric layer; attaching the waveguide to the position of the first dielectric layer; forming a first conductive member and a second conductive member over the waveguide, the first conductive member and the second conductive member being in contact with the waveguide; and etching a backside of the substrate to electrically expose the first and second conductive vias. The first conductive member or the second conductive member is electrically connected to the first or second conductive via.

Abstract: An IC package structure including an array of package units formed into a panel-shaped package units array. Each package unit has a continuous and closed metal wall surrounding the periphery of the package unit and at least one IC chip/IC die disposed in the package unit, and wherein each IC chip/IC die has a top surface and a back surface opposite to the top surface. A panel-shaped metal layer corresponding to the panel-shaped package units array can be formed on entire back side of the IC package structure and bonded to the metal wall of each package unit, wherein the back side of the IC package structure refers to the side to which the back surface of each IC chip/IC die is facing.

Abstract: A system for controlling of wafer bow in plasma processing stations is described. The system includes a circuit that provides a low frequency RF signal and another circuit that provides a high frequency RF signal. The system includes an output circuit and the stations. The output circuit combines the low frequency RF signal and the high frequency RF signal to generate a plurality of combined RF signals for the stations. Amount of low frequency power delivered to one of the stations depends on wafer bow, such as non-flatness of a wafer. A bowed wafer decreases low frequency power delivered to the station in a multi-station chamber with a common RF source. A shunt inductor is coupled in parallel to each of the stations to increase an amount of current to the station with a bowed wafer. Hence, station power becomes less sensitive to wafer bow to minimize wafer bowing.

Abstract: A package component for carrying a device package and an insulating layer thereon includes a molding layer, first and second redistribution structures disposed on two opposite sides of the molding layer, a semiconductor die, and a through interlayer via (TIV). A hardness of the molding layer is greater than that of the insulating layer that covers the device package. The device package is mounted on the second redistribution structure, and the insulating layer is disposed on the second redistribution structure opposite to the molding layer. The semiconductor die is embedded in the molding layer and electrically coupled to the device package through the second redistribution structure. The TIV penetrates through the molding layer to connect the first and the second redistribution structure. An electronic device and a manufacturing method thereof are also provided.

Abstract: A method for fabricating a semiconductor device includes forming a through-hole penetrating through an alternating stack pattern and forming a gap-fill layer, wherein a sacrificial gap-fill layer of the gap-fill layer fills the through-hole. The method also includes forming a mask layer over the alternating stack pattern and over the gap-fill layer, wherein the mask layer includes a self-aligned opening overlapping the filled through-hole and overlapping a portion of an uppermost material layer of the alternating stack pattern adjacent to the filled through-hole. The method further includes forming a first contact hole through the alternating stack pattern by performing a single etch using both the mask layer and the portion of the uppermost material layer as etch barriers to remove, through the self-aligned opening, the sacrificial gap-fill layer filling the through-hole.

Abstract: A semiconductor package includes a plurality of semiconductor chips. At least one of the semiconductor chips includes a semiconductor substrate including a semiconductor layer and a passivation layer having a third surface, a backside pad on the third surface, and a through-via penetrating through the semiconductor substrate. The backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding on one side of the electrode pad portion and surrounding a side surface of the through-via. The dam structure is spaced apart from the side surface of the through-via.

Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap.

Abstract: A parallel redundant system comprises a substrate, a first circuit disposed over the substrate, a first conductor disposed at least partially in a first layer over the substrate and wire routed to the first circuit, a second circuit disposed over the substrate, the second circuit redundant to the first circuit, a second conductor disposed in a second layer over the substrate and electrically connected to the second circuit, the second conductor disposed at least partially over the first conductor, a dielectric layer disposed at least partially between the first layer and the second layer, and a laser weld electrically connecting the first conductor to the second conductor.

Abstract: An integrated circuit (IC) package including ICs with multi-row columnar die interconnects has increased die-to-die (D2D) interconnect density in a conductive layer. Positioning the die interconnects in die interconnect column clusters, that each include a plurality of die interconnect rows and two columns, reduces the linear dimension occupied by the die interconnects and leaves room for more D2D interconnects. A die interconnect column cluster pitch is a distance between columns of adjacent die interconnect column clusters and this distance is greater than a die interconnect pitch between columns within the column clusters. Die interconnects may be disposed in the space between the multi-row column clusters and additional die interconnects can be disposed at the D2D interconnect pitch between the die interconnect column clusters. IC packages with ICs including the multi-row columnar die interconnects have a greater number of D2D interconnects for better IC integration.

Abstract: A heterostructure, such as a group III nitride heterostructure, for use in an optoelectronic device is described. The heterostructure can include a sacrificial layer, which is located on a substrate structure. The sacrificial layer can be at least partially decomposed using a laser. The substrate structure can be completely removed from the heterostructure or remain attached thereto. One or more additional solutions for detaching the substrate structure from the heterostructure can be utilized. The heterostructure can undergo additional processing to form the optoelectronic device.

Abstract: Devices, structures, materials and methods for carbon enabled vertical light emitting transistors (VLETs) and light emitting displays (LEDs) are provided. In particular, architectures for vertical polymer light emitting transistors (VPLETs) for active matrix organic light emitting displays (AMOLEDs) and AMOLEDs incorporating such VPLETs are described. Carbon electrodes (such as from graphene) alone or in combination with conjugated light emitting polymers (LEPs) and dielectric materials are utilized in forming organic light emitting transistors (OLETs). Combinations of thin films of ionic gels, LEDs, carbon electrodes and relevant substrates and gates are utilized to construct LETs, including heterojunction VOLETs.

Abstract: A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure.

Abstract: The present disclosure discloses an FPGA device forming a network-on-chip by using a silicon connection layer. An active silicon connection layer is designed inside the FPGA device. A silicon connection layer interconnection framework is arranged inside the silicon connection layer. Bare die functional modules inside an FPGA bare die are connected to the silicon connection layer interconnection framework to jointly form the network-on-chip. Each bare die functional module and a network interface and a router that are in the silicon connection layer interconnection framework form an NOC node. The NOC nodes intercommunicate with each other, so that the bare die functional modules in the FPGA bare die without a built-in NOC network can achieve efficient intercommunication by means of the silicon connection layer interconnection framework, reducing the processing difficulty on the basis of improving the data transmission bandwidth and performance inside the FPGA device.

Abstract: A semiconductor package includes a substrate including a first semiconductor chip including a first wiring structure, a first bonding pad, and a first alignment key on the first wiring structure to be spaced apart in a first direction, a second semiconductor chip including a second wiring structure, a second bonding pad on the second wiring structure and connected to the first bonding pad, and a second alignment key on the second wiring structure to be spaced apart from the second bonding pad and not overlapping the first alignment key in the second direction, the first wiring structure including a first wiring pattern connected to the first bonding pad and not overlapping the first and second alignment keys in the second direction, and the second wiring structure including a second wiring pattern connected to the second bonding pad and not overlapping the first and second alignment keys in the second direction.

Abstract: A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.