Abstract: An computer program instruction sequence control system to allow parallel or simultaneous execution of instructions. The system begins by loading two instructions for sequence determination. The system then checks if either instruction reads from or writes into the other instruction, if both instructions reference the same address, or if either instruction will contend with a currently executing instruction for the registers, arithmetic unit, or main memory. If no interference occurs, both instructions will be issued in parallel or simultaneously.

Abstract: A programmable element sequence selection circuit which selects a repeatable sequence of elements from a plurality of elements is provided. The sequence selection circuit includes a sequence storage circuit into which a sequence of element identifiers is loaded and accessed.

Abstract: An equipment for displaying a specification of behavior of a real time system includes a program memory for storing a plurality of program objects for simulating operations of objects indicative of an arrangement of the real time system and a plurality of graphical symbol objects for expressing operational states of the objects and relationships between the objects in the form of a graphical symbol representation on a display screen. In the equipment, the plurality of program objects are linked with the plurality of symbol objects through an inter-program communication control routine. Each of the program objects, when receiving a message from the communication control routine, is executed for simulation operation according to the received message to thereby generate a new message to be sent to the associated program routine and a new message indicative of an object state change to be sent to one of the symbol objects corresponding to the associated object.

Abstract: A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, accesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes.

Abstract: A scanning system using tree structures is constituted by a propagation operating unit array having a tree structure in which propagation units are formed into groups on each layer, and each group of the propagation operating units is connected to a propagation operating unit belonging to the higher adjacent layer, and an interface element array connected to the propagation operating units of the lowermost layer. Each of the propagation operating units is constituted by a plurality of cascaded propagation elements. Each propagation element includes first and second selectors for selecting input signals DA.sub.i and DB.sub.i from the lower adjacent layer in accordance with two propagation signals from the immediately forwarding propagation element and a third selector for selecting two propagation signals from an adjacent propagation element in accordance with an input signal U from the upper adjacent layer.

Abstract: A system for protecting data in a CPU's internal register. To obtain write access to the protected register, a process must sequentially write first and second keywords to an access register, within a predetermined time window.

Abstract: A program history (P-history) listing of branch-type instruction addresses for pipelined data processing system that employs one or more pipelined processors is stored in a random access memory (RAM) which is also used to store other executive or task information. A set of three queue registers is used to respectively store, 1) the absolute "to" address to which a branch instruction will jump, 2) the relative "to" address, to which the branch instruction will jump, and 3) the relative "from" address, from which the branch instruction will jump. The queues allow the storage of the P-history in the RAM without interference with the use of the RAM by the other functions that access it and without interruption of the pipelined processor.

Abstract: A common set of building block action modules perform specific tasks in the finite state machine and are strongly modular in structure. The set of building block action modules can be made up of modules for tasks generic to resource type and modules that are resource type independent. A finite state machine is created for each resource type to govern the steps of activation and deactivation of the resource. Each finite state machine, uniquely defines the new state and action processing for each resource type. To tie the building block action modules to each finite state machine, action vectors are created for each resource type. The action vector correlates a particular action selection by the finite state machine to the dispatching of one or more building block action modules. An action vector can contain a plurality of elements. Each of these elements identifies an action module to which control is passed and a function request pointer.

Abstract: A circuit for initializing a D-latch of an input/output system. The circuit comprises first and second logic means, the first logic means generating an enable signal coupled to the clock input of the D-latch which changes state from inactive to active at a first time t1 and again at a subsequent time t2, in response to the system write control signal addressed to the D-latch and the system reset signal. The second logic means generates a local data signal, in response to the system reset signal and system data signal, to the data input of the D-latch. The D-latch is reset substantially at time t1 and the system data signal is strobed in the D-latch substantially at time t2.

Abstract: A local net area network, or LAN, configuration is provided with a multiple generic LAN channel architecture which can be logically and dynamically changed. The configuration control can be applied to each module of the network and to each port of a module of a LAN hub. The architecture provides multiple LAN protocols to be used simultaneously, as needed, through protocol specific functions. Industry standard protocol such as: token bus, token ring, and fiber distributed data interface (FDDI), can be implemented using the generic channel architecture and its characteristics providing respective network functions. The architecture also provides a digital collision detection method and provides information necessary for precise network statistics monitoring. The token passing ring architecture provides a logical ring formation within the generic channel. A token passing bus architecture uses modified Ethernet.TM.

Abstract: A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a System Control Processor Interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. Control circuitry is also provided for setting the A20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse Keyboard Interface (MKI) is provided. The MKI provides even quicker switching of the Gate A20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.

Abstract: A data processing system includes a processor coupled to a system bus. A memory controller is also coupled to the system bus and to a memory bus in communication with a plurality of single in-line memory modules (SIMMs). Each SIMM comprises a plurality of DRAMS coupled to four cross bar switches (CBSs), such that address and data information is provided to the DRAMs through the cross bar switches. Each CBS includes a counter and decoder which controls a multiplexor. The multiplexor is coupled to enable ID logic, and four input registers (A.sub.R, B.sub.R, C.sub.R, D.sub.R), such that register A.sub.R is coupled to the output of the multiplexor, and the remaining registers are coupled to the input side of the multiplexor. An input buffer on the CBS is coupled to four input registers (A'.sub.W, B'.sub.W, C'.sub.W, D.sub.W). In addition, three of the input registers (A'.sub.W, B'.sub.W, C'.sub.W) are coupled to intermediate input registers A.sub.W, B.sub.W and C.sub.W.

Abstract: A virtual memory unit (VMU) includes a state machine for controlling its operations in response to commands received from another unit. The state machine includes a plurality of programmable array logic (PAL) devices which are connected to gather status from the different sections of the unit. The outputs of the PAL devices connect in common and supply a first address input to an addressable state memory. The state memory includes a plurality of locations, each of which stores a binary code defining a different machine state. The state memory locations are accessed as a function of the status signals and current state and used in turn to generate the required subcommands for executing the received commands. The state machine makes it possible to easily classify the received commands to their complexity and urgency in terms of their effect on overall system performance.

Abstract: The invention establishes the context in which data exchanged between dissimilar relational database management systems can be mutually understood and preserved. The invention accomplishes this by establishing layers of descriptive information which isolate machine characteristics, levels of support software, and user data descriptions. Optimized processing is achieved by processing the different descriptor levels at different times during the development and execution of the database management systems. Minimal descriptive information is exchanged between the cooperating database management systems. For systems which match, data conversion is completely avoided. For systems which do not match, data conversion is minimized.

Abstract: A cache system having a plurality of read-in ports through which data fetched from a main memory system can be transferred regardless of the type of the data fetch request. Further, each data fetch request is output from an available read-in port, during the data fetch operation for a previous data fetch request of the same type.

Abstract: A method and apparatus for storing and rewriting programs in an IC card. The system provides for storing programs in subdivided portions identified by attribute information including a program number, size and address. The system enables the rewriting of constituent elements of programs without the need for rewriting larger portions. The information identifying the programs parts is stored in an attribute information table in which said sub-area discrimination information and said management information are stored in combination.

Abstract: An EEPROM programming circuit is disclosed which provides for the on-board rogramming of a EEPROM memory using:a microprocessor, a bootstrap ROM, a UART communications port, and a Eccles-Jordan flip flop switch system. These elements are electrically connected to a host system and the EEPROM by a central data bus. In normal operation, the host system sends a first set of data signals through the circuit to the EEPROM, which produces a set of processed signals. In operation in the programming mode the host system sends a second set of data signals to cause the microprocessor to send a switch signal to the Eccles-Jordan flip flop switch and to the bootstrap ROM. The bootstrap ROM contains the program code that forms the programs that are used to program the EEPROM.

Abstract: The present invention provides a microprocessor with a special OEM mode of operation that can be used by an OEM system integrator to implement special tasks such as power management. The OEM mode provided by the present invention is designed for use by a system integrator who integrates a microprocessor into a larger system such as a personal computer. The OEM mode of operation provided by this invention adds features to the overall system; however, it is transparent to system programmers. The system integrator can use the OEM mode to configure a system so that the system has certain special power management features, which can not be accessed by programmers who use the system. The OEM mode provided by the present invention is accessed by a signal on a special I-O pin. For example, an external timer can periodically provide signals to this special pin, thereby periodically interrupting the microprocessor and putting the microprocessor in the OEM mode.

Abstract: The present invention provides for at least two levels of buffering in compensating for the delays from and out of the Unix workstation, thus achieving the required timebase correction. At the first level of buffering there is an eight Megabyte memory coupled to the VME bus of the Unix workstation over a disc simulator processor, which is sufficient to store about 45 seconds of audio data. The secondary level of data buffering is provided by an interface board which further buffers an additional 1.5 milliseconds between the first level of buffering and the second level of buffering. The outbound interface of the present invention comprises three separate registers to process the compact disc data when they are retrieved from the digital computer. Each of the registers comprises a plurality of FIFO registers. The first register receives outbound audio samples. The second register receives Q subcode data. The third register receives optionally QRSTUVW or RSTUVW subcode data.

Abstract: A device providing pointing device functions in a keyboard without requiring the keyboard operator to remove any fingertip from the keys. A computer keyboard keyswitch mounting plate is supported for horizontal displacement against a resistive force. A transducer for measuring the force exerted in the plane of the keyboard key tops is attached between the keyboard case and the keyswitch mounting plate. The direction and magnitude of the force can be measured and encoded so they may be used to emulate the signals generated by a pointing device. The operator may elect a pointing device mode by merely applying sufficient force along the plane of the surface of the key tops, thus switching from a keyboard mode to a pointing device mode, without moving the fingers from a typing position.