Abstract: Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.

Abstract: In a general aspect, a quantum information processing circuit is analyzed. In some implementations, a linear response function of a quantum information processing circuit is generated. A linear circuit model is generated based on the linear response function. A composite circuit model is generated by combining the linear circuit model and a nonlinear circuit model. An operating parameter of the quantum information processing circuit is computed by solving the composite circuit model. In some implementations, an electromagnetic structure solver determines the linear response function based on a circuit specification, a quantum circuit analysis tool calculates the operating parameters, and the circuit specification is modified based on the operating parameters.

Abstract: In a DC-DC voltage conversion device, overheat of a diode element connected in anti-parallel with a semiconductor switching element is a problem, and in order to resolve this, a temperature of a semiconductor switching element of a main conversion circuit is detected, a temperature of a diode element connected in parallel with the semiconductor switching element is calculated using a correction calculation of the detected semiconductor switching element temperature value in accordance with a step-up ratio of the DC-DC voltage conversion device, and diode element overheat protection is carried out in accordance with the calculated temperature value.

Abstract: A method of performing a charging function by using different types of energy sources and an electronic device thereof are provided. The electronic device includes different types of circuits configured to acquire different types of energy sources, and a processor configured to determine an energy source for charging among the different types of energy sources based on respective current values for the different types of energy sources, and control the determined energy source for charging so as to be used in battery charging of the electronic device or in a system operation of the electronic device.

Abstract: Embodiments include methods, design layout optimization systems, and computer program products for optimizing design layout of integrated circuits.

Abstract: Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. The circuit stencils include collapsed versions of the connectivity information of components and nodes of the integrated circuit. The collapsed version of the connectivity information is generated by analyzing functionality of the circuit segment and removing or replacing at least one redundant component or node of the circuit segment without modifying the functionality. The circuit stencil is used for instantiating or referencing components into a second integrated circuit.

Abstract: A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.

Abstract: Techniques and mechanisms for marking the parameters of a circuit analysis process for visual identification are disclosed. The visually-identified parameters can then be employed with the results of the circuit analysis to debug the layout design.

Abstract: Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.

Abstract: The invention relates to wireless energy transfer systems wherein electromagnetic field is used to transfer energy over air. An apparatus of a wireless energy transfer system comprises an inductive energy transfer coil (43) comprising at least two adjacent wire turns, wherein said turns are arranged to be coupled to a battery (41) such that said turns vertically surround the battery (41) during inductive energy transfer. The invention further relates to a method for producing the apparatus and an electronic device comprising the apparatus.

Abstract: A mask fabricating method includes dividing an outline of a design layout into segments, setting comparison areas with respect to an evaluation point corresponding to each of the segments, for each segment, calculating an overlapping area between the design layout and each of the comparison areas, classifying the segments into groups based on the calculated overlapping areas, wherein segments having a characteristic of the same overlapping area are included in a first group, calculating bias values for each of the segments, obtaining a representative bias value for each group, for each group, assigning the representative bias value obtained for that group to each of its segments, updating the design layout based on the segments with their assigned representative bias values, and fabricating a mask based on the updated design layout.

Abstract: This application discloses a computing system implementing one or more tools or mechanism configured to capture a hierarchy of a circuit design layout generated by a downstream tool. The hierarchy can include multiple cells that identify corresponding portions of the circuit design layout. The tools or mechanism can be further configured to modify the circuit design layout based, at least in part, on the captured hierarchy, which alters the portions of the circuit design layout identified by the cells separately from other portions of the circuit design layout.

Abstract: A virtual hierarchical layer (VHL) is constructed for a semiconductor design in order to reduce the computational requirement of design rules checking (DRC) and design rules for manufacture (DRM) procedures. In order to form the VHL, a negative plane is created. A cell and multiple instances of the cell are then identified in the semiconductor design and polygons which overlap the cell and its instances are determined. The polygons are pushed into the negative plane to create holes in the plane. Shapes overlapping other instances of the cell which fall onto holes in the solid virtual cell plane are ignored. The resulting holed solid virtual cell plane can then be inverted to create a VHL to be used for design simulation and verification.

Abstract: Systems and methods for designing reconfigurable integrated circuits receive target data and training data; and generate a circuit design for implementing the target data which is over-provisioned with respect to the target data according to the training data.

Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.

Abstract: A method of mask correction where two independent process models are analyzed and co-optimized simultaneously. In the method, a first lithographic process model simulation is run on a computer system that results in generating a first mask size in a first process window. Simultaneously, a second hard mask open etch process model simulation is run resulting in generating a second mask size in a second process window. Each first lithographic process model and second hard mask open etch process model simulations are analyzed in a single iterative loop and a common process window (PW) optimized between lithography and etch is obtained such that said first mask size and second mask size are centered between said common PW. Further, an etch model form is generated that accounts for differences in an etched pattern due to variation in three-dimensional photoresist profile, the model form including both optical and density terms that directly relate to an optical image.

Abstract: Disclosed are techniques for implementing DRC clean multi-patterning process nodes with lateral fills. These techniques identify design rules governing multi-patterning and track patterns by accessing a rule deck to retrieve the design rules, identify a first shape and a second shape sandwiching a space and characteristics of the first and second shapes by examining design data of the electronic design, insert one or more lateral fill shapes in the space by implementing the one or more lateral fill shapes along one or more routing tracks of a legal track pattern while automatically complying with the design rules, and perform post-lateral fill or post-layout operations to improve the layout and to prepare the layout for manufacturing.

Abstract: An emulator emulating a DUT emulates a clock generator for generating clock signals of the DUT with jitter. As part of generating clock signals, the emulator generates a jitter clock value for each clock signal. To generate a jitter clock value for a clock signal, the emulator identifies a clock parameter stored for the clock signal and sums the clock parameter with a jitter value randomly selected from the jitter range of the clock signal. When a system fast clock cycle starts, the emulator determines the lowest value from the generated jitter clock values. The emulator outputs an edge on clock signal having the lowest jitter clock value. The emulator generates a new jitter clock value for each clock signal and the process repeats during the next system fast clock cycle.

Abstract: An apparatus for controlling a battery of a green car, the apparatus includes an information collector configured to collect navigation information; a charge amount manager configured to manage a charge amount of the battery; a charger configured to charge the battery; and a controller configured to control the charging according to the charge amount of the battery and to expand a usable state of charge range of the battery based on the navigation information collected by the information collector.

Abstract: A method includes receiving from a user, via a user interface, coverage-event characteristics. Using a processor, output data of test runs executed on a device-under-test is analyzed to identify one or a plurality of coverage events that possess the coverage-event characteristics and to identify one or a plurality of contributing test runs in said test runs that contributed to said one or a plurality of coverage events. Information on said one or a plurality of contributing test runs is outputted via an output device.