Abstract: A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.

Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.

Abstract: A display unit includes a display panel including a display region and a terminal region on a first substrate, the display region including a plurality of pixels, each of the plurality of pixels including a light emitting element, and the terminal region including a plurality of terminals at a part of a peripheral region of the display region. The light emitting element includes a first electrode, an organic layer, and a second electrode that is provided commonly to the plurality of pixels, in order from the first substrate side. The second electrode extends, continuously in a plan view, to an end of the first substrate in a region on the first substrate except for the terminal region, and is configured to be electrically disconnected from an exterior member of the display panel.

Abstract: In case of performing annealing at a temperature of 1300° C. or higher, it is not possible to sufficiently suppress escape of nitrogen from a GaN layer even if a cap layer is provided thereon. Thereby, the front surface of the GaN layer is roughened. A semiconductor device manufacturing method of manufacturing a semiconductor device having a nitride semiconductor layer is provided. The semiconductor device manufacturing method includes: implanting, into a predetermined region of the nitride semiconductor layer, n-type or p-type impurities relative to the nitride semiconductor layer; forming, by atomic layer deposition, a first protective film containing a nitride on and in direct contact with at least the predetermined region; and annealing the nitride semiconductor layer and the first protective film at a temperature of 1300° C. or higher.

Abstract: A method of fabricating a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer overlies the interconnect structure and includes a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.

Abstract: A display may have an array of pixels formed from thin-film transistor circuitry. The thin-film transistor circuitry may include thin-film layers of dielectric, semiconductor, and metal on a dielectric substrate. Test structures may be formed around the periphery of the substrate to facilitate testing of the thin-film circuitry during manufacturing. The test structures may include test pads that are coupled to the thin-film circuitry by test lines extending from the thin-film circuitry. Following testing, the outermost portions of the display and the test pads on these display portions may be removed by cutting the substrate along a substrate cut line. The test lines may be formed from parallel lines that are shorted together, semiconductor layers, multiple layers of conductive material, and other structures that resist corrosion along the cut line.

Abstract: A display apparatus is disclosed. The display apparatus includes a substrate, a display, and a protective film. The substrate includes a bending area between a first area and a second area and is bent about a bending axis. The display is over an upper surface of the substrate in the first area. The protective film is over a lower surface of the substrate. The protective film includes a first protective film base over the lower surface of the substrate and corresponding to at least a part of the first area, and a first adhesive layer between the substrate and the first protective film base. The first protective film base includes a first thick portion having a first thickness and a first thin portion having a second thickness less than the first thickness and is closer to the bending area than the first thick portion.

Abstract: A light emitting diode includes: an n-type nitride semiconductor layer; an active layer over the n-type nitride semiconductor layer; and a p-type nitride semiconductor layer over the active layer. The n-type nitride semiconductor layer includes: an n-type nitride layer; a first intermediate layer over the n-type nitride layer; an n-type modulation-doped layer over the first intermediate layer. The light emitting diodes includes a second intermediate layer over the n-type modulation-doped layer. The second intermediate layer includes a sub-layer having a higher n-type doping concentration that an n-type doping concentration of the n-type modulation-doped layer.

Abstract: A display device includes a substrate divided into an encapsulation area and a non-encapsulation area. The display device includes an interlayer insulating layer disposed over the substrate. The display device includes a first inner contact hole passing through the interlayer insulating layer in the encapsulation area, and connecting an inner conductive layer to an inner lower conductive layer. The display device includes an outer contact hole passing through the interlayer insulating layer in the non-encapsulation area, and connecting an outer conductive layer to an outer lower conductive layer. A slope angle formed by a lateral wall of the outer contact hole with respect to an upper surface of the substrate is less than a slope angle formed by a lateral wall of the first inner contact hole with respect to the upper surface of the substrate.

Abstract: An OLED display is disclosed. In one aspect, the display includes a first TFT formed over a substrate and including a gate electrode and a second TFT electrically connected to the first TFT. A gate bridge is formed over the gate electrode and configured to electrically connect the gate electrode and the second TFT, the gate bridge connected to the gate electrode through a contact hole formed over the first TFT. A capacitor electrode is formed over the gate bridge, an insulating layer is interposed between the capacitor electrode and the gate bridge, and the capacitor electrode, the insulating layer, and the gate bridge form a capacitor. An OLED is electrically connected to the first TFT.

Abstract: Systems, media, and methods for modeling electronic products for 3D printing including providing a library of modules and module interfaces; receiving at least one ruleset; receiving preliminary substrate structure data, the preliminary substrate structure data comprising shape and volume data defining a substrate; providing an interface allowing the user to place one or more modules on the substrate; providing an interface allowing the user to place one or more module interfaces, the module interfaces coupling one or more modules together through the substrate; warning the user where placement of a module or module interface violates the at least one ruleset; generating routing of electrically conductive interconnects between placed module interfaces; and generating a finalized substrate structure model by combining the preliminary substrate structure data with module placement data and interconnect routing data.

Abstract: A thin film transistor substrate includes: a plurality of pixels arranged in a matrix, each of the pixels including: a thin film transistor including: a gate electrode made of a metal and disposed on the substrate; a gate insulating film covering at least the gate electrode; a semiconductor layer including an oxide semiconductor provided at a position facing the gate electrode with the gate insulating film interposed therebetween; a source electrode and a drain electrode in contact with the semiconductor layer; and an interlayer insulating film provided on at least the semiconductor layer, the source electrode, and the drain electrode; and a pixel electrode electrically connected to the drain electrode. The gate electrode has hydrogen occlusion capability of 2.5×1020 to 2×1022 atoms/cm3, and the semiconductor layer has a hydrogen concentration of 1×1016 atoms/cm3 or less.

Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

Abstract: An organic light-emitting display device, including a substrate that includes a plurality of first emission portions that realize a first color and a plurality of second emission portions that realize a second color; a pixel-defining film that defines the plurality of first emission portions and the plurality of second emission portions; a plurality of pixel electrodes that are separate from each other and respectively correspond to the plurality of first emission portions; and a first stacked structure that includes an intermediate layer and a counter electrode on the intermediate layer, the intermediate layer including an organic emission layer emitting light of the first color, the first stacked structure further including first emission pattern portions respectively corresponding to the plurality of first emission portions, and first connection pattern portions on the pixel-defining film, the first connection pattern portions connecting the first emission pattern portions.

Abstract: An epitaxial layer is formed by epitaxy on a base substrate at a front side. From opposite to the front side, at least a portion of the base substrate is removed, wherein the base substrate is completely removed or a remnant base section has a thickness of at most 20 ?m. Dopants of a first charge type are implanted from opposite of the front side into an implant layer of the epitaxial layer. A metal drain electrode is formed opposite to the front side. At least the implant layer is heated to a temperature not higher than 500° C. The heating activates only a portion of the implanted dopants in the implant layer. After heating, an integrated concentration of activated dopants along a shortest line between the metal drain electrode and a closest doped region of a second, complementary charge type is at most 1.5E13 cm?2.

Abstract: A multiple silicon trenches forming method and an etching mask structure, the method comprises: step S11, providing a MEMS sealing cap silicon substrate (100); step S12, forming n stacked mask layers (101, 102, 103) on the MEMS sealing cap silicon substrate (100), after forming each mask layer, photolithographing and etching the mask layer and all other mask layers beneath the same to form a plurality of etching windows (D1, D2, D3); step S13, etching the MEMS sealing cap silicon substrate by using the current uppermost mask layer and a layer of mask material beneath the same as a mask; step S14, removing the current uppermost mask layer; step S15, repeating the step S13 and the step S14 until all the n mask layers are removed.

Abstract: Embodiments of the present invention disclose an array substrate comprising a base substrate and a plurality of pixel units disposed on the base substrate, the pixel unit comprising a transflective layer formed on the base substrate; a thin film transistor structure formed over the transflective layer; an organic light-emitting diode disposed in a pixel region of the pixel unit and driven by the thin film transistor structure, and in a direction away from the base substrate, the organic light-emitting diode sequentially comprising a first electrode that is transparent, an organic light-emitting layer and a second electrode for reflecting light; and a color filter, disposed between the second electrode of the organic light-emitting diode and the transflective layer; wherein the second electrode of the organic light-emitting diode and the transflective layer constitute a microcavity structure.

Abstract: An organic light emitting display panel is provided that comprises a substrate comprising an emission area and a non-emission area; a black matrix disposed on the non-emission area and comprising at least one open area that exposes at least a portion of a pattern formed on the substrate, wherein the pattern or the exposed portion of the pattern comprises a multi-layer structure comprising a conductive layer and at least one low reflective layer.

Abstract: The present disclosure relates to an Organic Light-Emitting Diode (OLED) apparatus and a method for manufacturing the same. The OLED apparatus comprises an OLED device, a device packaging layer, an upper flexible substrate, and a lower flexible substrate, wherein an anti-reflection layer is arranged outside the upper flexible substrate, and a layer of inorganic nanoparticles is provided on a surface of the anti-reflection layer. Using the technical solution of the present disclosure, an OLED apparatus which has both waterproof and anti-reflection effects and a small overall thickness is obtained.

Abstract: The present application discloses a semiconductor device in which an IGBT region and a diode region are formed on one semiconductor substrate. The IGBT region includes: a collector layer; an IGBT drift layer; a body layer; a gate electrode; and an emitter layer. The diode region includes: a cathode layer; a diode drift layer; an anode layer; a trench electrode; and an anode contact layer. The diode region is divided into unit diode regions by the gate electrode or the trench electrode. In a unit diode region adjacent to the IGBT region, when seen in a plan view of the front surface of the semiconductor substrate, the anode layer and the anode contact layer are mixedly placed, and the anode contact layer is placed at least in a location opposite to the emitter layer with the gate electrode interposed therebetween.