Abstract: In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.

Abstract: Disclosed is a processor chip that includes on-chip and off-chip software. The chip is optimized for hyperdimensional, fixed-point vector algebra to efficiently store, process, and retrieve information. A specialized on-chip data-embedding algorithm uses algebraic logic gates to convert off-chip normal data, such as images and spreadsheets, into discrete, abstract vector space where information is processed with off-chip software and on-chip accelerated computation via a desaturation method. Information is retrieved using an on-chip optimized decoding algorithm. Additional software provides an interface between a CPU and the processor chip to manage information processing instructions for efficient data transfer on- and off-chip in addition to providing intelligent processing that associates input information to allow for suggestive outputs.

Abstract: An optical phased array comprising a row-column driving mechanism is disclosed that reduces the number of digital to analog converter (DAC) channels to the number of rows N and the total number of interface pin counts down to the number of columns plus the number of rows M+N. Disclosed herein are systems and architecture for thermal waveguide-based phase shifters which improve thermal efficiency by having multi-pass waveguides arranged proximate a heating element in a serpentine fashion, which enables an increase in phase shift without increasing the length or the power consumption of the heating element by increasing the total length of waveguide being heated by a singular heating element.

Abstract: A data compression method comprises encoding groups of data items by generating, for each group, header data comprising h-bits and a plurality of body portions each comprising b-bits and each body portion corresponding to a data item in the group. The value of h may be fixed for all groups and the value of b is fixed within a group, wherein the header data for a group comprises an indication of b for the body portions of that group. In various examples, b=0 and so there are no body portions. In examples where b is not equal to zero, a body data field is generated for each group by interleaving bits from the body portions corresponding to data items in the group. The resultant encoded data block, comprising the header data and, where present, the body data field can be written to memory.

Abstract: A method of integrated circuit includes: providing a non-volatile memory circuit for securely and permanently recording and protecting key data content having Y bits; providing a programmable memory circuit for storing user configuration data content having X bits greater than Y bits; converting the user configuration data content having X bits into user configuration key content having Y bits; comparing the user configuration key content having Y bits with the key data content having Y bits; selecting fallback configuration data content having X bits as output data when the user configuration key content does not match the key data content; selecting the user configuration data content having X bits as the output data when the user configuration key content matches the key data content; and receiving the output data of the decision circuit and performing at least one corresponding capability operation according to the output data.

Abstract: An antenna apparatus includes a patch antenna pattern; a first feed via to feed power to the patch antenna pattern in a non-contact manner on a first side of the patch antenna pattern; and a plurality of feed patterns disposed on the first side of the patch antenna pattern on different levels and overlapping each other, and including at least one feed pattern that is electrically connected to the first feed via, and each having a width greater than a width of the first feed via and a cross-sectional area smaller than a cross-sectional area of the patch antenna pattern.

Abstract: A successive approximation analog-to-digital converter includes a digital-to-analog converter DAC configured to receive a digital signal. First conversion units of the DAC are configured to sample an analog signal via a first switch and provide a first level voltage. Each first conversion unit includes a first capacitor array and a first switch array controlled from the digital signal. A single second conversion unit of the DAC is configured to provide a second level voltage. The second conversion unit includes a second capacitor array and a second switch array. A comparator operates to compare each of the first level voltages to the second level voltage and to provide a comparison signal based on each comparison and actuation of a set of third switches. A control circuit closes the first switches simultaneously and closes the third switches successively for the conversion of each sampled analog signal.

Abstract: An information handling system includes a processor configured to process a training data file to determine an optimal data compression algorithm. The processor may also perform a compression ratio analysis that includes compressing the training data file using data compression algorithms, calculating a compression ratio associated with each of the data compression algorithms, determining an optimal compression ratio from the compression ratio associated with the each data compression algorithm; and determining a desirable data compression algorithm associated with the training data file based on the optimal compression ratio.

Abstract: This application discloses a temperature feedback control apparatus, method. The method includes two electric switches, a feedback control unit and an optical component. A first electric switch is configured to control that only a first channel of at least two channels that correspond to the first electric switch is conducted at a moment, to feed back an optical signal of a target optical component connected to the first channel to the feedback control unit. The feedback control unit is configured to calculate temperature of the corresponding optical component based on an electrical signal converted from the optical signal, to obtain a control signal. The second electric switch is configured to control, when the first channel is conducted, that only the second channel is conducted, to transmit the control signal to the target optical component to adjust its temperature. The optical component connects to both the first and second channels.

Abstract: A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.

Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 8-bits using a technique that is selected dependent upon the values of the MSBs of the 10-bit values and setting the value of an HDR flag dependent upon the values of the MSBs. The HDR flag is appended to the 3-bit channel.

Abstract: A method of an electronic device includes: providing a capacitive digital-to-analog converter having a reference voltage input; providing a reference voltage providing circuit to generate a reference voltage to the reference voltage input of the capacitive digital-to-analog converter; and, generating a compensation signal into the reference voltage input of the capacitive digital-to-analog converter in response to at least one switching of at least one capacitor in a switchable capacitor network of the capacitive digital-to-analog converter.

Abstract: A three-dimensional data encoding method includes: generating an N-ary tree structure of three-dimensional points included in three-dimensional data, where N is an integer greater than or equal to 2; generating first encoded data by encoding a first branch using a first encoding process, the first branch having, as a root, a first node included in a first layer that is one of layers included in the N-ary tree structure; generating second encoded data by encoding a second branch using a second encoding process different from the first encoding process, the second branch having, as a root, a second node included in the first layer and different from the first node; and generating a bitstream including the first encoded data and the second encoded data.

Abstract: A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.

Abstract: An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.

Abstract: An analog-to-digital converter (ADC) and an operation method thereof are provided. The ADC includes: a comparator which compares a signal input through a first input terminal and a signal input through a second input terminal, and outputs an output value according to the comparison result. A successive approximation register receives the output value of the comparator, sets digital signal values from a most significant bit to a least significant bit, and outputs the digital signal values. A digital-to-analog converter receives the digital signal values, and converts it into an analog signal based on a reference voltage Vref, and outputs it to the second input terminal. A noise component is added to the input signal and to the analog signal Vdac?.

Abstract: A method, which is applied in a driving circuit including an analog-to-digital convertor (ADC) and a switching circuit including an inductor and coupled to a load, includes steps of: performing an analog-to-digital conversion on a load voltage of the load at a first rate; and producing at least a current pulse flowing through the inductor at a second rate. Wherein, each current pulse among the at least a current pulse is accomplished within a second cycle corresponding to the second rate, all of the at least a current pulse are accomplished within a first cycle corresponding to the first rate, and a first length of the first cycle is longer than twice of a second length of the second cycle.

Abstract: A calibration system comprises an actuator circuit comprising a first delay circuit that receives a plurality of data pulses and a second delay circuit that receives the pulses, wherein one of the first and second delay circuits delays the data pulses independently of the other of the first and second delay circuits; a data switch that receives an output of the actuator circuit including delay data signals of the data pulses from the first and second delay circuits and switches and outputs a plurality of local oscillator (LO) signals for output as a controlled LO signal according to control signals of the delay data signals and applied to the data switch. At least one calibration switch receives the output of the actuator circuit and the plurality of LO+ and LO? signals, and outputs a second controlled LO signal output to a sense circuit.

Abstract: A circuit system for weight modulation and image recognition of a memristor array includes a personal computer (PC), a field-programmable gate array (FPGA) chip, a digital-to-analog conversion unit, a switch unit, a memristor array unit, an integration and signal amplification circuit, and an analog-to-digital converter. The circuit system selects a to-be-realized function such as array reading and writing, weight modulation or image recognition, converts a command or an RGB value of an image collected by the PC into a corresponding grayscale value, and sends the grayscale value to the FPGA chip. The FPGA chip controls and selects a to-be-modulated memristor array unit through the digital-to-analog conversion unit and the switch unit. An application program of the PC controls the FPGA chip in real time to realize array reading and writing, weight modulation, and image recognition, and then the FPGA chip displays a result on the PC in real time.

Abstract: The present application discloses an analog-to-digital converter capable of cancelling sampling noise, which comprises: a sampling circuit configured to acquire an analog input signal; a sampling noise cancelling circuit has an input end connected with an output end of the sampling circuit, and is configured to cancel noise generated by the sampling circuit; a comparator has an input end connected with an output end of the sampling noise cancelling circuit, and an output end connected with an input end of a logic circuit, and is configured to compare magnitudes of output signals of the sampling noise cancelling circuit and output a comparison result to the logic circuit; and the logic circuit has an output end connected with the sampling circuit, and is configured to output a digital output signal, and process the comparison result to obtain a control signal by which an output voltage of the sampling circuit is controlled.