Patents Examined by Long Pham
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Patent number: 11999027Abstract: A method for polishing a semiconductor substrate includes the following operations. A semiconductor substrate is received. An abrasive slurry having a first temperature is dispensed to a polishing surface of a polishing pad. The semiconductor substrate is polished. The abrasive slurry have a second temperature is dispensed to the polishing surface of the polishing pad during the polishing of the semiconductor substrate. The second temperature is different from the first temperature.Type: GrantFiled: August 8, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: James Jeng-Jyi Hwang, He Hui Peng, Jiann Lih Wu, Chi-Ming Yang
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Patent number: 12002786Abstract: A semiconductor package includes a first semiconductor chip mounted on a substrate, a first conductive post disposed on the substrate and spaced apart from the first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and the first conductive post, and a mold layer on the substrate that covers the first and second semiconductor chips and the first conductive post. The second semiconductor chip is supported on the first semiconductor chip by a first dummy solder terminal provided between the first and second semiconductor chips, and is coupled to the first conductive post by a first signal solder terminal provided between the first conductive post and the second semiconductor chip. The first dummy solder terminal is in direct contact with a top surface of the first semiconductor chip, and is electrically disconnected from the second semiconductor chip.Type: GrantFiled: November 26, 2021Date of Patent: June 4, 2024Assignee: Samsung Electronics Co., Ltd.Inventor: Young Lyong Kim
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Patent number: 12002771Abstract: A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device further includes a dielectric layer over the conductive pad, wherein the dielectric layer has a first conformity. The semiconductor device further includes a passivation layer over the dielectric layer, wherein the passivation layer has a second conformity different from the first conformity.Type: GrantFiled: May 13, 2021Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lung Shih, Chao-Keng Li, Alan Kuo, C. C. Chang, Yi-An Lin
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Patent number: 12002729Abstract: A electronic package and a method of manufacturing the same are provided. The electronic package includes an electronic component, a thermal spreading element, and an encapsulant. The electronic component has a first surface. The thermal spreading element is disposed over the electronic component and has a first surface facing the first surface of the electronic component. The encapsulant covers the electronic component and has a first surface closer to the first surface of the thermal spreading element than the first surface of the electronic component.Type: GrantFiled: July 30, 2021Date of Patent: June 4, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: You-Lung Yen, Bernd Karl Appelt
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Patent number: 12002742Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.Type: GrantFiled: June 13, 2022Date of Patent: June 4, 2024Assignee: MEDIATEK INC.Inventors: Tzu-Hung Lin, Yuan-Chin Liu
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Patent number: 11996379Abstract: A filter package structure includes: a die substrate, a substrate, a solder resist layer, a package layer, and a conductive structure disposed; wherein the solder resist layer is disposed on the substrate, and a plurality of channels are formed in the solder resist layer, each of the channels being provided with a solder; the conductive structure includes a seal wall and a support electrode, the seal wall and one terminal of the support electrode being connected to the substrate via the solder; and the die substrate is provided with a filter, wherein the seal wall is disposed around a periphery of the filter, the die substrate, the substrate and the seal wall enclose to define an enclosed chamber, the support electrode is disposed in the enclosed chamber, and the package layer is disposed on a periphery, far away from the enclosed chamber, of the die substrate.Type: GrantFiled: September 22, 2023Date of Patent: May 28, 2024Assignee: GUANGZHOU AIFO LIGHT COMMUNICATION TECHNOLOGY COMPANY LTD.Inventor: Guoqiang Li
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Patent number: 11984412Abstract: An electronic package in which at least one magnetically permeable member is disposed between a carrier and an electronic component, where the electronic component has a first conductive layer, and the carrier has a second conductive layer, such that the magnetically permeable element is located between the first conductive layer and the second conductive layer. Moreover, a plurality of conductive bumps that electrically connect the first conductive layer and the second conductive layer are arranged between the electronic component and the carrier to surround the magnetically permeable member for generating magnetic flux.Type: GrantFiled: January 17, 2023Date of Patent: May 14, 2024Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien Chiu, Ko-Wei Chang
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Patent number: 11973017Abstract: A multilayer package substrate includes a plurality of dielectric layers including a top dielectric layer on a top side and a bottom dielectric layer on a bottom side. A top patterned metal layer is on the top dielectric layer and a bottom patterned metal layer is on the bottom dielectric layer. At least one of the top dielectric layer and the bottom dielectric layer is a porous dielectric layer having a plurality of pores including an average porosity of at least 5% averaged over its thickness.Type: GrantFiled: October 20, 2021Date of Patent: April 30, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jaimal Mallory Williamson, Jim C Lo
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Patent number: 11967566Abstract: A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.Type: GrantFiled: December 21, 2022Date of Patent: April 23, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vijaylaxmi Gumaste Khanolkar, Robert Martinez, Zhemin Zhang, Yongbin Chu
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Patent number: 11967525Abstract: Embodiments of the disclosure relate to methods of depositing tungsten. Some embodiments of the disclosure provide methods for depositing tungsten which are performed at relatively low temperatures. Some embodiments of the disclosure provide methods in which the ratio between reactant gasses is controlled. Some embodiments of the disclosure provide selective deposition of tungsten. Some embodiments of the disclosure provide methods for depositing tungsten films at a low temperature with relatively low roughness, stress and impurity levels.Type: GrantFiled: August 1, 2022Date of Patent: April 23, 2024Assignee: Applied Materials, Inc.Inventors: Yi Xu, Yufei Hu, Yu Lei, Kazuya Daito, Da He, Jiajie Cen
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Patent number: 11961800Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.Type: GrantFiled: July 21, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh
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Patent number: 11955455Abstract: A method includes bonding a first package component over a second package component. The second package component includes a plurality of dielectric layers, and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes dispensing a stress absorber on the second package component, curing the stress absorber, and forming an encapsulant on the second package component and the stress absorber.Type: GrantFiled: July 25, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shin-Puu Jeng, Chien-Sheng Chen, Po-Yao Lin, Po-Chen Lai, Shu-Shen Yeh
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Patent number: 11956938Abstract: A device incudes a substrate. A first fin and a second fin are over the substrate. An isolation structure is laterally between the first fin and the second fin. A gate structure crosses the first fin and the second fin. A first source/drain epitaxy structure is over the first fin. A second source/drain epitaxy structure is over the second fin. A spacer layer extends from a first sidewall of the first fin to a first sidewall of the second fin along a top surface of the isolation structure.Type: GrantFiled: June 28, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tetsu Ohtou, Ching-Wei Tsai, Kuan-Lun Cheng, Yasutoshi Okuno, Jiun-Jia Huang
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Patent number: 11948895Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.Type: GrantFiled: July 4, 2022Date of Patent: April 2, 2024Assignee: MEDIATEK INC.Inventors: Tzu-Hung Lin, Chia-Cheng Chang, I-Hsuan Peng, Nai-Wei Liu
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Patent number: 11948904Abstract: A die includes a substrate, a conductive pad, a connector and a protection layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector includes a seed layer and a conductive post. The protection layer laterally covers the connector. Topmost surfaces of the seed layer and the conductive post and a top surface of the protection layer are level with each other.Type: GrantFiled: March 21, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
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Patent number: 11948975Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.Type: GrantFiled: October 24, 2021Date of Patent: April 2, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
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Patent number: 11950477Abstract: The present application discloses an OLED display panel, including a plurality of first color sub-pixels, a plurality of second color sub-pixels, and a plurality of third color sub-pixels, wherein the first-color subpixels, the second-color subpixels, and the third-color subpixels constitute a plurality of repeating units, the repeating units include a first repeating unit and a second repeating unit, and the first repeating unit and the second repeating unit are arranged at intervals in any row or any column.Type: GrantFiled: April 28, 2020Date of Patent: April 2, 2024Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Di Zhang
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Patent number: 11948839Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.Type: GrantFiled: November 1, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng
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Patent number: 11948854Abstract: An electronic component includes a substrate, a functional portion, external connection conductor portions, and first and second heat-conducting portions. The functional portion is located on first principal surface of the substrate and portion generates heat during operation. The external connection conductor portions are located directly on the first principal surface of the substrate or located below the first principal surface without direct contact with the substrate. The second principal surface of the substrate includes first and second regions. When viewed in plan in a thickness direction of the substrate, the first region does not overlap the functional portion, and the second region coincides with the functional portion. The first heat-conducting portion is located directly on all or a portion of the first region or located over all or a portion of the first region without direct contact with the substrate.Type: GrantFiled: May 10, 2021Date of Patent: April 2, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Masato Nomiya
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Patent number: 11942385Abstract: A semiconductor package includes a substrate having a first side and a second side opposite to the first side, a first type semiconductor die disposed on the first side of the substrate, a first compound attached to the first side and encapsulating the first type semiconductor die, and a second compound attached to the second side, causing a stress with respect to the first type semiconductor die in the first compound. A method for manufacturing the semiconductor package described herein is also disclosed.Type: GrantFiled: March 29, 2022Date of Patent: March 26, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Sheng-Yu Chen, Chang-Lin Yeh, Ming-Hung Chen