Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.

Abstract: A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm. A second sealing material is provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm.

Abstract: The stack type package module includes a plurality of stacked tape carrier packages. Each package has an elongated lead having an extension end connected to the first lateral end connected to a central portion connected to a second lateral end. The second lateral end is connected to the respective chip via a bump. The packages made as such are then stacked on top of each other on a printed circuit board. The plurality of the stacked first lateral ends are then cut and soldered the printed circuit board. The predetermined portions of the packages including the cut first lateral ends are sealed for protection.

Abstract: A contact structure, including: a first conductive layer; a insulating layer formed on the first conductive layer; a second conductive layer formed on the insulating layer; and a columnar structure, buried in a direction of film thickness in the insulating layer, electrically connecting the first conductive layer and the second conductive layer; wherein a reinforcement material is adhered to a vicinity of a root of the columnar structure.

Abstract: According to this invention, a method for fabricating a semiconductor package, in which a plurality of semiconductor chips having a through electrode is layered on a semiconductor interposer, comprising: mounting and layering a plurality of semiconductor chips on a first surface of a semiconductor wafer, which is to be used for a semiconductor interposer; forming a mold resin over the semiconductor chips to cover the semiconductor chips entirely; and dicing the semiconductor wafer to form a plurality of individual semiconductor packages.

Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Abstract: A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a second opposing surface thereof. Each of the first and second pluralities of bond pads includes an under-bump metallization (UBM) layer. The singulated semiconductor die is disposed on a semiconductor die site of a semiconductor wafer and a first plurality of conductive bumps electrically couples the first plurality of bond pads of the singulated semiconductor die with a first set of bond pads formed on the semiconductor die site. A second plurality of conductive bumps is disposed on a second set of bond pads of the semiconductor die site. A third plurality of conductive bumps is disposed on the singulated semiconductor die's second plurality of bond pads. The second and third pluralities of conductive bumps are configured for electrical interconnection with an external device.

Abstract: In a method and an apparatus for dividing a plate-like member related to the present invention, multiple substrates are obtained by forming a linear modified region on a surface of a plate-like member formed from a hard and brittle material or in the interior of the plate-like member and dividing the plate-like member along this modified region. The method for dividing a plate-like member includes a tape sticking step which involves sticking tape on the surface of the plate-like member, a modified region forming step which involves forming a modified region on surface of the plate-like member or in the interior of the plate-like member, and an expanding step which involves elongating the tape by applying a tension thereto after the modified region forming step. In the expanding step, the tape is irradiated with UV rays. As a result of this, it is possible to positively manufacture an ultrathin chip with a good end-face shape in which uncut portions, chipping and breakage do not occur.

Abstract: A structure for improving the electrostatic discharge robustness of an integrated circuit having an electrostatic discharge (ESD) device and a receiver network connected to a pad by interconnects. The interconnect between the pad and the ESD device has a high-k material placed adjacent to at least one surface of the interconnect and extending over the thermal diffusion distance of the interconnect. The high-k material improves the critical current density of the interconnect by increasing the heat capacity and thermal conductivity of the interconnect. The high-k material can be placed on the sides, top and/or bottom of the interconnect. In multiple wire interconnects, the high-k material is placed between the wires of the interconnect. A low-k material is placed beyond the high-k material to reduce the capacitance of the interconnect. The combination of low-k and high-k materials provides an interconnect structure with improved ESD robustness and low capacitance that is well suited for an ESD device.

Abstract: A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool.

Abstract: A method of simultaneously bonding components, comprising the following steps. At least first, second and third components are provided and comprise: at least one glass component; and at least one conductive or semiconductive material component. The order of stacking of the components is determined to establish interfaces between the adjacent components. A hydrogen-free amorphous film is applied to one of the component surfaces at each interface comprising an adjacent: glass component; and conductive or semiconductive component. A sol gel with or without alkaline ions film is applied to one of the component surfaces at each interface comprising an adjacent: conductive or semiconductive component; and conductive or semiconductive component. The components are simultaneously anodically bonded in the determined order of stacking.

Abstract: An improved window frame and window piece for a micromirror assembly is disclosed herein. The window frame includes a stress-relieving contour positioned in the middle of the frame that can absorb the mechanical stresses applied to the window frame from the ceramic base and from the window piece. The window frame may be comprised of a single piece of sheet metal that has been stamped to include a stress-relieving contour. The stress-relieving contour may be comprised of a variety of shapes, including a “U” shape, an inverted “U” shape, a curved step shape, or other combinations thereof.

Abstract: A folded frame carrier has a die attach pad (DAP) 30 and one or more folded edges 32, 33, 34, 35. Each folded edge has one or more studs 36 and each stud has a trapezoidal tip. The folded frame carrier may be made of single gauge copper or copper alloy. Multiple folded frame carriers may be formed between opposite rails of a lead frame. The folded edges are cut with a relief groove. The tips are formed in edges of the DAP and then the tips are folded upright. The tips provide electrical connection to the terminal on the rear surface of a power semiconductor mounted on the DAP.

Abstract: This method of manufacturing a lid made of a transparent resin comprises a step of introducing a resin into a cavity for molding a protrusion continuous with a cavity for molding a lid in a die; a step of forming a molded body including a lid and a protrusion continuous with the lid by solidifying the resin in the cavity for molding a lid and the cavity for molding a protrusion, respectively; a step of separating the molded body from the die by ejecting an ejector pin to the protrusion; and a step of separating the protrusion from the lid.

Abstract: A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire include triple layers of an adhesion layer, a Ag containing layer and a protection layer. The adhesion layer includes one of Cr, Cr alloy, Ti, Ti alloy, Mo, Mo alloy, Ta and Ta alloy, the Ag containing layer includes Ag or Ag alloy, and the protection layer includes one of IZO, Mo, Mo alloy, Cr and Cr alloy.

Abstract: A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.

Abstract: Disclosed are integrated circuit assemblies with increased stand-off height and methods and systems for their manufacture. Methods of the invention provide for assembling a semiconductor device by aligning a die with a substrate and interposing solder between corresponding substrate and die bond pads. A lifting force is applied to the die during heating of the solder to a liquescent state, thereby increasing the stand-off height of the die above the substrate. The lifting force is maintained during cooling of the solder to a solid state, thereby forming increased stand-off height solder connections.

Abstract: This invention generally relates to methods and apparatus for connecting to an integrated circuit die, in particular where the die includes both analogue/microwave radio frequency (rf) circuitry and digital circuitry. A method of connecting a die having both microwave radio frequency (rf) circuitry and digital circuitry to a substrate of a package for the die, the die having a plurality of bond pads, some for said rf circuitry and some for said digital circuitry, the substrate having a plurality of interconnects for making external connections to said package and a plurality of substrate pads for connecting said interconnects to said die, the method comprising: connecting at least one of said bond pads for said rf circuitry to a substrate pad by connecting said rf bond pad to an intermediate substrate and connecting said intermediate substrate to said substrate pad. Preferably at least some of the bond pads for the digital circuitry are directly connected to the substrate pads, for example by wire bonding.

Abstract: A method for stacking and bonding wafers in precision alignment by detecting alignment marks provided on wafer edges, comprising the steps of: (a) providing at least a first wafer having at least a first pattern and at least a second pattern disposed on the cross-section thereof, at least a second wafer having at least a third pattern and at least a fourth pattern disposed on the cross-section thereof, and at least a sensing device, while pairing the first pattern with the third pattern and pairing the second pattern with the fourth pattern; (b) actuating the first wafer and the second wafer for enabling the first to parallel the second wafer and to be a distance apart from the second wafer; (c) actuating the first wafer and the second wafer for bringing the two wafers to move toward each other while enabling the sensing device for detecting and determining whether or not the first pattern is in a position capable of matching with the third pattern and the second pattern in another position capable of matchin

Abstract: Disclosed is a semiconductor apparatus including: a first molded resin portion; a plate-shaped lead frame closely attached to the first molded resin portion; a second molded resin portion attached facing the first molded resin portion and the lead frame; and one or more elements attached on the lead frame on a side which faces the second molded resin portion, the one or more elements including a semiconductor element, wherein any part of at least one of the elements does not exist in a region composed of an aggregation of line segments, each line segment being formed by any two points on an outer periphery of the plate-shaped lead frame outside the first and second molded resin portions and all of the line segments being contained inside a board of the lead frame.