Patents Examined by Lynnne A. Gurely
  • Patent number: 6518184
    Abstract: A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: February 11, 2003
    Assignee: Intel Corporation
    Inventors: Stephen T. Chambers, Valery M. Dubin, Andrew W. Ott, Christine S. Hau-Riege