Abstract: A single instruction is received to read a read address in storage in order to obtain read data and write the read data to a write address in the storage. Error correction decoding is performed in order to obtain user data. Error correction parity information is generated based at least in part on (1) the user data and (2) new metadata associated with the write address, without buffering the user data between the error correction decoding and the generation of the error correction parity information. The user data, the new metadata, and the error correction parity information are stored in the write address in the storage.

Abstract: According to one embodiment, a non-volatile semiconductor storage apparatus is configured to decide determination periods respectively corresponding to each of management blocks based on rewrite count information items and a temperature, and to perform a determination processing for each of management blocks for each determination period. The determination processing includes determining whether first data read from a block in the blocks is normal based on the number of errors that are occurred in the first data. The apparatus is configured to perform a rewrite processing of rewriting the first data to second data which is error-corrected when it is determined that the first data is not normal.

Abstract: A method for delocalizing an error checking on a data in a pipelined processor from the data checked. A first check-data is generated at a first location on a first data. A second location receives the first data and the first check-data. A second check-data is generated on the first data and the first check-data is compared with the second check-data at the second location. A second data is generated from the first data and a third check-data is generated on the second data at the second location. A third check-data is generated on the second data at the second location and the second data is transferred to a third location. The third check-data is transferred to a fourth location. A fourth check-data is generated on the second data and is transferred to the fourth location. The fourth check-data and the third check-data are compared at the fourth location.

Abstract: A packet data transmitting method and mobile communication system using the same enables transmission of common ACK/NACK information from each sector of a base station to a user entity in softer handover. The method includes receiving via at least one of the plurality of sectors a data packet from the mobile terminal, the data packet being correspondingly received for each of the at least one of the plurality of sectors; combining the correspondingly received data packets, to obtain a signal having a highest signal-to-noise ratio; decoding the value obtained by the combining; determining a transmission status of the data packet according to the decoding; and transmitting to the mobile terminal a common ACK/NACK signal including one of a common ACK signal and a common NACK signal according to the determining, the common ACK/NACK signal being transmitted via each of the at least one sector.

Abstract: A method and wireless transmit/receive unit (WTRU) for uplink transmission are disclosed. A WTRU receives configuration information. The configuration information includes logical channel priority information and a maximum number of hybrid automatic repeat request (HARQ) transmissions. The WTRU receives an uplink grant for a transmission time interval (TTI). The WTRU identifies a HARQ process to use for uplink transmission for the TTI. The WTRU selects data for uplink transmission for the TTI. For a new uplink transmission, data associated with a highest priority is selected. The WTRU initializes a transmission counter. The transmission counter indicates a number of transmissions associated with the selected data. The WTRU transmits the selected data over an uplink channel based on the received uplink grant using the identified HARQ process.

Abstract: Techniques and mechanisms to provide selective access to data error information by a memory controller. In an embodiment, a memory device stores a first value representing a baseline number of data errors determined prior to operation of the memory device with the memory controller. Error detection logic of the memory device determines a current count of data errors, and calculates a second value representing a difference between the count of data errors and the baseline number of data errors. The memory device provides the second value to the memory controller, which is unable to identify that the second value is a relative error count. In another embodiment, the memory controller is restricted from retrieving the baseline number of data errors.

Abstract: A method and system to improve the link budget of a wireless system using fast Hybrid Automatic Repeat Request (HARQ) protocol. In one embodiment of the invention, the Medium Access Control (MAC) logic in a base station determines whether the quality of the communication link with a mobile station is bad. When the MAC logic in the base station determines that the quality is bad, the base station uses a fast Hybrid Automatic Repeat Request (HARQ) protocol to indicate to the mobile station to send identical information to the base station in each of a plurality of successive or consecutive communication intervals before processing any received identical information from the mobile station. The fast HARQ protocol reduces the latency of receiving the identical information correctly, as compared with the current HARQ protocol.

Abstract: A storage apparatus includes a processor. The processor is configured to sequence a plurality of data pieces. The plurality of data pieces are respectively stored in a plurality of memory devices. The processor is configured to set compensation ranges to be respectively compensated by a first predetermined number of parities. The compensation ranges are respective portions of consecutive data pieces among the sequenced data pieces. The compensation ranges include a variably set number of data pieces for the respective parities. Each of the plurality of data pieces is included in a second predetermined number of compensation ranges.

Abstract: A digital broadcasting system and method of processing data are disclosed. Herein, a method of processing data in a transmitting system includes creating a data group including a plurality of mobile service data packets, re-adjusting a relative position of at least one main service data packet of a main service data section, the main service data section including a plurality of main service data packets, and multiplexing the mobile service data of the data group and the main service data of the main service data section in burst units. Herein, a position of an audio data packet among the main service data packets of the main service data section may be re-adjusted. Also, a position of an audio data packet included in the main service data section may be re-adjusted based upon a multiplexing position of the main service data section.

Abstract: A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.

Abstract: The present application relates to an interconnect system comprising a video signal transmitter and video signal receiver for transmitting a stream of N-symbol data signals over an error prone wired parallel bus having at least N data signal lines. A line scrambler at the video signal transmitter is configured to accept an N-symbol data signal having a sequence of data symbols in a predefined order and to output a permuted sequence of data symbols in accordance with a permutation. The line de-scrambler at the video signal receiver is configured to accept the permuted sequence of data symbols at its input terminal and to restore the predefined order of data symbols from the permuted sequence of data symbols in accordance with the corresponding reverse permutation.

Abstract: The present application relates to an interconnect system for transmitting a stream of N-symbol data signals, which comprises a parallel data signal line bus, a line scrambler, a line de-scrambler and a defect detector. The defect detector is configured to detect one or more defective data signal lines. The line scrambler 110 is configured to accept an N-symbol data signal d having a sequence of data symbols in a predefined order and to output a permuted sequence d? of data symbols at its N output terminals oj. The line de-scrambler is configured to accept the permuted sequence d? of data symbols at its input terminal i?j, to restore the predefined order of the data symbols from the permuted sequence d? of data symbols; and to output the restored N-symbol data signal d comprising a sequence of data symbols in the predefined order.

Abstract: One example embodiment includes a circuit system. The system includes a wave-pipelined combinational logic circuit comprising at least one logic gate between an input node and at least one output node and configured to perform logic operations on a data sequence received at the input node. The system also includes a scan path connected to the input node and comprising at least one delay element configured to propagate the data sequence from the input to a scan path output to capture values of the data sequence provided to the wave-pipelined combinational logic circuit as a serial data stream. The system also includes a scan point device configured to deliver one of input data and scan data as the data sequence to the wave-pipelined combinational logic circuit and to the scan path via the input node in a respective one of a normal operating mode and a scan mode.

Abstract: A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet transmit circuit that employs a data framing module. The data framing module includes an input interface to receive Ethernet block data bits, and, forward error correction encoder is coupled to the logic to encode at least a first portion of the data bits to generate first error check bits. A Reed-Solomon (RS) encoder is coupled to the logic to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits. A symbol mapper modulates the Ethernet block data bits in accordance with an SQ64 constellation comprising back-to-back PAM8 symbols.

Abstract: In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus transmits, from two antennas, LDPC encoded data formed by LDPC encoding blocks. In a case of a retransmittal, the multi-antenna transmitting apparatus uses a transmission method, in which the diversity gain is higher than in the previous transmission, to transmit only a part of the LDPC encoded data as previously transmitted. For example, the only the part of the LDPC encoded data to be re-transmitted is transmitted from the single antenna.

Abstract: In a mobile communication system, an error detection code or a quality frame indicator (e.g., CRC) is generated using selectively frame information, and at least one of a WCA identifier of another terminal, and a corresponding terminal identifier. And the terminal identifier can be implicitly transmitted to the receiver.

Abstract: A method of transmitting broadcast signals includes forward error correction (FEC) encoding mobile data; interleaving the FEC encoded mobile data; encoding signaling information for the mobile data; mapping the interleaved mobile data and the encoded signaling information into a data unit, wherein the data unit includes a first region and a second region, wherein the first region is concatenated with the second region, wherein the first region includes known data and the encoded signaling information, and wherein the second region includes known data and the encoded mobile data; and transmitting the broadcast signals including the data unit, wherein the data unit is multiplexed with a data unit of main data in a specific time period, wherein the signaling information includes information of the data unit having the interleaved mobile data.

Abstract: The present invention relates to retransmissions In a communications system. A method and system of reducing uplink retransmission delay of a radio communications system by introducing an uplink MAC ARQ layer of Node B is disclosed. Further, a MAC PDU data indicator for soft combining control In Node B and RLC PDU reordering is introduced.

Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including writing first data to the memory, reading the first data from the memory, analyzing the first read data such that the analyzing includes determining whether the read data includes an error, encoding second data based on the analyzing of the first data such that the second data is encoded to be written to a position adjacent to the error when it is determined that the read data includes the error, and writing the encoded second data to the memory at the position.

Abstract: A stack type semiconductor apparatus may be provided. The stack type semiconductor apparatus may include a plurality of semiconductor chips stacked and configured for transferring signals through through-hole vias. Each of the plurality of stacked semiconductor chips may include an error detection circuit configured to perform a down scan for transferring a signal to a lower direction and an up scan for transferring a signal to an upper direction through through-hole vias in a column direction among the through-hole vias, and to determine whether the through-hole vias have failed according to a down scan result value and an up scan result value.