Abstract: The present invention relates to an apparatus for verifying a data path through a digital switch between a transmitting port and a receiving port. The apparatus comprises a transmitter which transmits a test data block in a first predetermined time slot which corresponds to the time slot associated with the transmitting port. A receiver receives the test data block in a second predetermined time slot, which corresponds to the time slot associated with the receiving port. Test logic examines the received test data block to determine that the test data block has been transmitted error-free through the digital switch thereby verifying the data path.

Abstract: In apparatus for error correction in which data sequences containing blocks of data, previously arranged on a known time-base, and formed of data words and check words are written into a memory under control of a write address generator, and the data sequences are subsequently read out from the memory under control of a write address generator, so as to generate rearranged data sequences; during writing and reading of the data sequences, error correction is carried out by apparatus that includes an error correction arithmetic circuit for performing the error correction calculation, a pointer addition circuit for adding a pointer to the data words in association with an error state of the blocks, and a memory for memorizing a microprogram having fields to control the error correction arithmetic circuit and pointer addition circuit.

Abstract: Disclosed is a control method for writing or reading sequentially a plurality of blocks of data for a storage device using a recording medium, such as a photo disk, with a number of recording blocks each having a unique address. In writing data, a plurality of data blocks to be written concurrently are given in their pointer fields the first address indicating the same alternative block, and these data are written in consecutive recording blocks on the recording medium. If blocks with write errors are detected, the data blocks corresponding to the error blocks are written sequentially in an alternative area starting from the first address, after replacing the pointer fields with the second address indicating the defective blocks, respectively. This allows the access of the alternative blocks for defective blocks by detecting the pointer address within the pointer fields of normal blocks preceding and following each of the defective blocks during the data reading operation.

Abstract: A function check of a programmable logic array is performed in which input lines, product term lines and ground lines are combined into an AND plane and output lines, product term lines and ground lines are combined into an OR plane. The aim is a simple method of function check which permits any potentially-existing fault to be detected. The check is achieved by generating, with a test data generator, bit patterns and applying the same to the input lines, and, through the use of a shift register, successively sensitizing the product term lines either individually or in groups, i.e. disconnecting the same from ground potential. The bit patterns occurring at the output lines are supplied to a test data evaluator. The area of use is in logic circuitry of data processing technology.

Abstract: A branch metric processor for use in a maximum-likelihood convolutional decoder accepts a set of soft-decision symbols, an indicator of a level of quantization thereof and a set of erase control signals and generates branch metrics for base code rates of 1/3 and 1/2. The apparatus represents a substantial reduction in complexity over prior art devices. Erasure of selected symbols allows the processor to generate branch metrics for higher code rates and is advantageous in very low code rate applications.

Abstract: The selecting system makes use of a bank of amplifiers for successively and sequentially exciting P different types of integrated circuits assembled together in groups. The amplifying channels are periodically enabled one after the other by means of a demultiplexing circuit controlled from a processing and programming unit designated as PPU. The direct-current supplies comprise a programmable supply which is also addressed by the PPU and the output of which is applied to a switching matrix, the matrix being also addressed by the PPU and connected via P outputs respectively to the P groups of integrated circuits. Transmission of the excitation signals to the group of integrated circuits relating to said signals is performed by means of a second switching matrix addressed by the PPU. A mass memory unit such as a microprocessor is associated with the PPU and can have an electric functional test program for programming the excitation signals desired for selection.

Abstract: A method and system for loading test data into individual pin memories of an automatic digital test system, particularly of the in-circuit type. Test data in the form of test vectors are accessed from a test vector store simultaneously with the access of a digital test pin selection signal. The test pin selection signal accessed with the test data is then used to selectively load the test data into a pin memory identified by the pin selection signal, thereby permitting the loading of test data into any one of a group of individual pin memories. In the preferrred embodiment the test data, a test vector, is stored in a test vector store in association with a test pin selection signal. When the test vector is read from memory, the test pin selection signal is also read by the same address signal.

Abstract: A line printer which comprises a standard type-belt (1) having a plurality of character sets (2), clock (CL) marks for individual characters, and home position (HP) marks for each character set. Further, the line printer comprises a belt image memory (13') for storing the character codes of the characters of the type-belt (1). Flag bits are inserted at positions of the belt image memory (13') corresponding to the reference marks of the character sets (2). Further, the output (HP-D) of the belt image memory (13') is compared with the output (HP) of the type-belt (1) to perform a belt synchronous check.

Abstract: A fail-safe protection circuit for a data processor controlled system having a data bus for carrying data and comprising first logic for checking the operation of the data processor controlled system at periodic intervals not greater than T.sub.1 and for producing a trigger pulse at each check if the data processor is operating properly, second logic for detecting the absence of trigger pulses for a time period T.sub.2 to produce a control signal. Gating logic is responsive to the control signal to prevent the transmission of data through the data bus and a control circuit is also responsive to the control signal to reset the system to a predetermined operating state. The first logic responds to the resetting of the system to again produce the periodic trigger pulses if the system is operating properly.

Abstract: A single error correcting memory is constructed from partially good components on the design assumption that the components are all-good. Those small number of logical lines containing double-bit errors are replaced when detected with good lines selected from a replacement area of the memory. The replacement area is provided by a flexibly dynamically deallocated portion of the main memory so that it can be selected from any section of the original memory by inserting the appropriate page address in the replacement-page register. With such a memory architecture until the first double-bit error is detected (either in testing or actual use) all pages may be used for normal data storage. When such an error is detected some temporarily unused page in the memory is deal-located, that is rendered unavailable for normal storage, and dedicated to providing substitute lines. The same procedure is followed for subsequent faults.

Abstract: Apparatus consisting of combinations of interconnected logic elements for generating preselected sequences of addresses for the listing of a matrix memory as a function of preset constants and variable timing impulses, wherein there are first and second X and Y address generators with controlled selection means for selecting the first or the second of the X and Y address pairs, each of the address generators being settably controllable to generate a preselected sequence of addresses in ascending or descending order, with settable increments within the sequence, settable masking, and settable displacements from a fixed reference origin.