Abstract: Provided are a display device with low power consumption which enables reduction of an operation processing amount of a GPU and which does not require a storage device for storing image data corresponding to one screen, and a display system using the display device. The display device is constituted by pixels each including storage circuits, an operation processing circuit, and a display processing circuit and circuits each having a function of storing image data in arbitrary storage circuits. The display system is constituted by the display device and an image processing device including the GPU. Image data is formed for each structural component through operation processing in the GPU in the display system. The formed image data is stored in the corresponding storage circuit for each pixel. The stored image data is subjected to composition processing by the operation processing circuit for each pixel. Then, the image data is converted into an image signal in the display processing circuit.

Abstract: Systems and methods for balancing a load among multiple graphics processors that render different portions of a frame. A display area is partitioned into portions for each of two (or more) graphics processors. The graphics processors render their respective portions of a frame and return feedback data indicating completion of the rendering. Based on the feedback data, an imbalance can be detected between respective loads of two of the graphics processors. In the event that an imbalance exists, the display area is re-partitioned to increase a size of the portion assigned to the less heavily loaded processor and to decrease a size of the portion assigned to the more heavily loaded processor.

Abstract: Methods and apparatus for implementing a pixel page system providing pixel pages optimized for use with a GLV (grating light valve). In one implementation, a system includes: a data source, providing pixel data for pixels in a first order, each pixel in a frame having rows and columns of pixels; a data destination, receiving pixel data for pixels in a second order; at least one memory device including memory pages having memory locations; pixel data for each pixel corresponds to an entry in a pixel page, each pixel page having rows and columns and including pixels, the pixel pages optimized for use with a GLV. Pixel data is stored to memory in the first order and retrieved in the second order. And each memory page stores pixel data in multiple locations according to the first order and stores pixel data in multiple locations according to the second order.

Abstract: Methods and apparatus for implementing a pixel page system providing swapped pixel pages for use with a GLV (grating light valve).

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes an image processor. The image processor includes an image signal processor having two or more processing elements. The processing elements concurrently process an array of pixel values via a plurality of image filter comparison operations.

Abstract: Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations.

Abstract: An image processing apparatus is provided that includes a primary memory unit to buffer image data, a secondary memory unit to store the image data transferred from the primary memory unit, and a memory control unit that controls both memory units. The memory control unit transfers, if a plurality of items of image data are to be transferred, at least one of the items of image data divisionally from the primary memory unit to the secondary memory unit. When image data are transferred from the primary memory unit to the secondary memory unit, the memory control unit transfers a unit image either in a block or divisionally in multiple parts, and the memory control unit simultaneously transfers a plurality of images divisionally, the images being divided into varying numbers of parts so that each input and output of an image can evenly share the time of the secondary memory unit and a plurality of images can be efficiently transferred in parallel in a short time.

Abstract: A method of storing a texel in a texel cache comprising reading a t coordinate of the texel, the t coordinate comprising a plurality of bits, reading a s coordinate of the texel, the s coordinate comprising a plurality of bits, forming an offset by concatenating bits of the t coordinate with bits of the s coordinate and forming an index by concatenating bits of the t coordinate with bits of the s coordinate and at least one bit of a level of detail is discussed.

Abstract: A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

Abstract: A graphics memory includes a plurality of memory partitions. A memory controller organizes tile data into subpackets that are assigned to subpartitions to improve memory transfer efficiency. Subpackets of different tiles may be further assigned to subpartitions in an interleaved fashion to improve memory operations such as fast clear and compression.

Abstract: A control device, which is capable of suppressing an increase in a load of a data transfer for an increase of an amount of data is provided. The control device includes a compressed data generation unit for generating a compressed data based on a set-up value inputted, and a controller for outputting a frame rate information to the compressed data generation unit, and for making compressed data to be outputted from a memory for use in storing a compressed data to an image display device in accordance with the frame rate.

Abstract: A system and methods are provided for processing graphics to be displayed in a portable device. A current mode of operation of the portable device is identified. In a normal mode of operation, image data associated with the portable device is rendered by a graphics system of the portable device and stored in memory external to the graphics system prior to display. When a screen refresh mode of operation is identified, image data rendered by the graphics system is compressed and stored in memory integrated internal to the graphics system. The present disclosure has the advantage of allowing the memory external to the graphics system to be disabled during the screen refresh mode of operation, reducing power consumed by the portable device.

Abstract: A system and method are disclosed for improving the remote display of graphics images by the redirection of rendering and the optional use of image data compression. Instead of sending graphics commands over a network and rendering on a remote computer system, graphics commands may be automatically redirected by modified OpenGL functions to local graphics devices without explicit involvement by the graphics application. The modifications to a set of the OpenGL functions on the local system are transparent in the normal mode of rendering and displaying locally. After an image is rendered locally, it may be read back and sent across the network. A standard X Server on the remote system may be sufficient to support this methodology. An X Extension for data decompression on the remote system, however, may allow for more efficient image transmission through the use of image data compression.

Abstract: Conventionally, in displaying a document on a display, the document is displayed on the display after an image of the document is drawn off-screen once. Thus, it may take long until the image of the document can be checked when it is drawn for the first time. In an image processing apparatus of this invention, every time a predetermined number of drawing elements among drawing elements included in document data are developed off-screen, it is checked whether or not the developed off-screen drawing elements satisfy intermediate drawing conditions and, when it is determined that the intermediate drawing conditions are satisfied, the developed off-screen drawing elements are drawn on the display.

Abstract: A resampling circuit and method where input sample values for samples arranged along a row of a source image are received by a row resampling circuit. The row resampling circuit calculates row output values which are provided to a column resampling circuit that calculates output sample values therefrom. The column resampling circuit includes a shift register that receives the row output values and shifts the row output values through the shift register as the row output samples are calculated. The shift register has a plurality of evenly spaced sample output terminals from which the row output values are sampled by an interpolation circuit for calculation of the output sample values.

Abstract: The method of one embodiment for the invention is for the CPU to read a subset of consecutive pixels from RAM and cache each such pixel in the WC Cache (and load corresponding blocks into the L2 Cache). These reads and loads continue until the capacity of the L2 Cache is reached, and then these blocks (a “band”) are iteratively processed until the entire band in the L2 Cache has been written to the frame buffer via the WC Cache. Once this is complete, the process then “dumps” the L2 Cache (that is, it ignores the existing blocks and allows them to be naturally pushed out with subsequent loads) and the next band of consecutive pixels is read (and their blocks loaded). This process continues until the portrait-oriented graphic is entirely loaded.

Abstract: An apparatus, executing on a server or similar machine and a client machine, and a corresponding method, includes mechanisms for rendering a two-dimensional image of a three-dimensional object, and streaming the thus-rendered image to the client machine. The mechanisms include a rendering module that generates a first image, from a first point of view, having a plurality of pixels, as first image data for display on a client machine, and generates first depth information for one or more of the plurality of pixels, and a compression module that compresses the first image data and the first depth information, wherein the first image data and the first depth information are provided to the client machine.

Abstract: An image rendered by a non-alpha-channel-aware application is employed in an alpha-channel-aware environment. The pixel data file to be written to by the non-alpha-channel-aware application is initialized by setting the alpha value for each pixel to 1. The alpha-channel-aware application then writes to the initialized pixel data file, changing some or all pixel data. The alpha value for each pixel is then decremented by 1 (modulo 256) making the changed pixels opaque and the unchanged pixels transparent.

Abstract: A programmable graphics system and method for processing high precision graphics data represented in one or more data formats in one or more passes. Graphics program instructions executed by the system control the processing and format conversion of the data. The program instructions and the data are stored in a memory accessible by the system. Within the memory, contiguous memory entries can contain program instructions or data represented in different formats. The format used to represent a particular data element within the data, is specified in the state information maintained in the system and is used to configure format conversion units within the system. High precision data, such as floating color, is processed by the programmable graphics system and output via a digital to analog converter (DAC) for display.

Abstract: An address converting unit receives pixel coordinates of a display screen in sequence and converts the received pixel coordinates to addresses and offsets. The addresses and offsets obtained from the conversions are stored in buffers in sequence respectively. A buffer controlling unit detects that one of the buffers is full. In response to the detection by the buffer controlling unit, a pixel processing unit modifies pixel data corresponding to the plural addresses read from the memory device according to pixel information. The pixel data stored in the memory device are rewritten according to the pieces of pixel information inputted in correspondence with the pixel coordinates. Therefore, the pieces of pixel data corresponding to the plural addresses are rewritten at a time.