Abstract: A method of forming a multi-layer suicide gate structure for a MOS type semiconductor device that includes the processing steps of first providing a substrate, then depositing a gate oxide layer on the substrate, then depositing a first refractory metal silicide layer which has a first stoichometry on the gate oxide layer, and finally depositing a second refractory metal silicide layer which has a second stoichometry different than the first stoichometry on the first deposited refractory metal silicide layer.

Abstract: An improved method and structure is provided for integrating HSQ and other low dielectric constant materials, which may have undesirable properties, into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. The present invention combines the advantages of SiO.sub.2 and low dielectric constant materials by creating a multilayer dielectric stack of alternating layers of low-k materials and traditional dielectrics. A stabilizing layer is inserted between layers of low-k films. Since the thickness of problematic low-k materials remain less than the cracking threshold, many of the problems discussed above are alleviated. The stabilizing prevents the nucleation and propagation of micro cracks. In a preferred embodiment, interconnect lines 14 are first patterned and etched on a substrate 10. A low-k material such as hydrogen silsesquioxane (HSQ) 18 is spun across the surface of the wafer to fill areas between interconnect lines.

Abstract: Disclosed is the use of silicon carbide as a barrier layer to prevent the diffusion of metal atoms between adjacent conductors separated by a dielectric material. This advancement allows for the use of low resistivity metals and low dielectric constant dielectric layers in integrated circuits and wiring boards.

Abstract: A semiconductor device includes a connection pad layer for securing a contact margin which is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. A device fabricated according to this structure yields improved punch-through and junction depth characteristics.

Abstract: In accordance with the invention, an integrated circuit has a first ESD protection circuit for each input pin which is not adjacent a non-wired IC pin and a second ESD protection circuit for each input pin which is adjacent a non-wired pin. The second ESD protection circuit has a greater ESD protection capability than the first ESD protection circuit. The second ESD protection circuit has a capability of protecting an input pin when an ESD stress occurs at an adjacent non-wired pin. The second ESD protection circuit includes, for example, additional ESD protection elements in comparison to the first ESD protection circuit. Alternatively, the second ESD protection circuit has one ESD protection element which is larger in size or is otherwise different than a corresponding ESD protection element in the first ESD protection circuit.

Abstract: In an arrangement for signal transmission between chip layers of a vertically integrated circuit, a defined, capacitive signal transmission ensues between a part of the vertically integrated circuit in one chip layer and a further part of the vertically integrated circuit in a further chip layer by means of a coupling capacitance. Particularly given high connection densities, a large number of freely placeable and reliable vertical signal connections can be produced directly from the inside of one chip layer to the inside of a neighboring chip layer without extremely high demands being made on the adjustment of the chip layers relative to one another and on the surface planarity of the individual chip layers.

Abstract: An optical semiconductor assembly including a metal stem, a hermetic glass substrate fixed to the stem, and a conductive float pad formed on the hermetic glass substrate. The first to third leads are mounted to the stem so as to be insulated from the stem and pass through the stem. An optical semiconductor element is mounted on a lead head of the third lead, and a bare chip IC is mounted on the stem. By using the float pad, screening of the optical semiconductor element is performed during assembly. After completing the assembly, the characteristics of the assembly are checked to thereby perform screening of the bare chip IC. Thus, two independent steps of screening are performed, so that improvement in yield of the completed products can be expected.

Abstract: A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.

Abstract: A self scanning light-emitting array is disclosed. A coupled array of light-emitting elements is constituted so that a light-emitting element in a minimal conducting state influences the next light-emitting element so that its threshold level is changed. When each element is driven by a common clock pulse, the change in threshold level is shifted in the longitudinal direction, so that a minimal conducting state is transferred in a clock period of the clock pulse.

Abstract: With regard to paired drive transistors, the shape of an active area is (point or line) symmetrical to a channel area in the vicinity of the channel area. With regard to paired transfer transistors, likewise, the shape of a word line is (point or line) symmetrical to the channel area in the vicinity thereof. With this structure, even if a gate electrode (word line) should be misaligned, therefore, the shapes of the channel areas of the paired transistors would become identical, so that there would be no difference between characteristics.

Abstract: A semiconductor device includes an interlevel film constituted by a first dielectrics film containing dangling bonds and a bonded group of Si and hydrogen, and a second dielectrics film formed on the first dielectrics film.

Abstract: Generally, according to the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material. One embodiment of the present invention is a microelectronic structure comprising a supporting layer having a principal surface, and an adhesion layer overlying the principal surface of the supporting layer, wherein the adhesion layer comprises a top surface and an expanded, oxidized sidewall (e.g. TiO.sub.2 40).

Abstract: An electronic package which contains discrete resistive and capacitive components used to control the operating device of an integrated circuit located within the package. The package has a bonding shelf that has a plurality of bond fingers which are connected to the integrated circuit. The discrete passive components are mounted to the bonding shelf and connected to the bond fingers by lead traces. The lead traces terminate at the discrete devices so that the resistor and capacitor cannot be accessed through the external contacts of the package. The integrated circuit and discrete components are typically enclosed by a molded plastic material to prevent physical access to the devices without damaging the package.

Abstract: A semiconductor chip packaging device includes a lead frame electrically connected to the chip and mechanically supporting the chip; a metal layer guard ring formed along at least one peripheral edge of an active surface of the chip; at least one slit formed at corner parts of the chip; a passivation layer covering the metal layer guard ring, the chip and the lead frame; and a package body made of a molding resin encapsulating the passivation layer, the lead frame, the metal layer and the chip; the metal layer guard ring being chamfered or rounded at corner parts of the chip to reduce shear stresses at the corner parts of the chip.

Abstract: A method for soldering a first component having a metal surface to a second component having a metal surface includes holding the metal surface of the first component in a position above a placement area on the metal surface of the second component to establish a gap between the surfaces. The method further includes reflowing solder within the gap.A structure including a thermally conductive baseplate, an electrical insulator attached to the baseplate, and a metallic shield mounted on the insulator. The structure also includes an integrated power device having a power-dissipating electronic device, and a first metal layer connected to the shield through a solder joint. A substrate includes an aperture, and the integrated power device is mounted with the power-dissipating device sitting within the aperture. The substrate also includes a conductive run electrically connected to a second metal layer of the integrated power device.

Abstract: A method for forming an interconnect for making a temporary or permanent electrical connection to a semiconductor dice is provided. The method includes forming a substrate with an insulating layer and a pattern of conductors thereon. The conductors are formed as a bi-metal stack including a barrier layer formed of an inert metal and a conductive layer formed of a highly conductive metal. Microbumps are formed on the conductors by deposition through a mask using an electroplating, electroless plating, screen printing or evaporation process. The interconnect can be used to provide a temporary electrical connection for testing bare semiconductor dice. Alternately the interconnect can be used for flip chip mounting dice for fabricating multi chip modules and other electronic devices.

Abstract: The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz->2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the signal path. In a preferred aspect of the invention, the SCR is assembled in the N-well of the Bipolar/BiCMOS device, as opposed to the P-substrate, as is customary in the prior art. A preferred aspect of the invention utilizes a Zener diode in combination with a resistor to control BSCR operation through the NPN transistor.

Abstract: One kind or plural kinds of elements selected from a groups III, IV or V elements are introduced in an amorphous silicon film, and then crystallized by heating at 600.degree. C. or less. The crystallization develops from a region where the element has been introduced in a direction parallel to a substrate. An active region of a semiconductor device is formed in a portion of the crystallized semiconductor layer in such a manner that the relation between the crystal growth direction and the direction in which the electric current of the device is selected in accordance with a desired mobility of the active region.

Abstract: A dual level transistor integrated circuit and a fabrication technique for making the integrated circuit. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed upon a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate. The integrated circuit further includes a first transistor. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric.

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60,97) that can be used to transport electrical signals across the device (10).