Patents Examined by Maki Angadi
  • Patent number: 9530626
    Abstract: A plasma processing method and apparatus are provided in which current spikes associated with application of a voltage to an electrostatic chuck (ESC) are minimized or reduced when the processing plasma is present. According to an example, the voltage is applied to the ESC after the processing plasma is struck, however the voltage is ramped or increased in a step-wise manner to achieve the desired final ESC voltage. In an alternate embodiment, the ESC voltage is at least partially applied before striking of the plasma for processing the wafer. By reducing current spikes associated with application of the voltage to the ESC during the presence of the processing plasma, transfer or deposition of particles on the wafer can be reduced.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: December 27, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jason Marion, Sonam Sherpa, Sergey A. Voronin, Alok Ranjan, Yoshio Ishikawa, Takashi Enomoto
  • Patent number: 9524876
    Abstract: Disclosed is a plasma etching method including a deposition process and an etching process. For a processing target object including a base layer and a photoresist having a predetermined pattern which are laminated in sequence, the deposition process deposits a protective layer including silicon and carbon on the photoresist of the processing target object by plasma of a first processing gas including silicon tetrachloride gas, methane gas, and hydrogen gas. The etching process etches the base layer by plasma of a second processing gas using the photoresist including the protective layer deposited thereon, as a mask. The second processing gas is different from the first processing gas.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: December 20, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toru Hisamatsu, Masanobu Honda
  • Patent number: 9524877
    Abstract: A dry etching method according to the present invention is for etching a silicon layer as a processing target in a processing room, characterized by supplying an iodine heptafluoride-containing etching gas from a gas supply source at a supply pressure of 66 kPa to 0.5 MPa, evacuating the processing room to an internal pressure lower than the supply pressure of the etching gas and, while maintaining the etching gas at the supply pressure, introducing the etching gas into the evacuated processing room so as to etch the silicon layer by the etching gas. It is possible by this dry etching method to etch the silicon upon adiabatic expansion of the etching gas under mild pressure conditions, with no fear of equipment load and equipment cost increase, and achieve good uniformity of in-plane etching amount distribution.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: December 20, 2016
    Assignee: Central Glass Company, Limited
    Inventors: Akiou Kikuchi, Isamu Mori, Masanori Watari
  • Patent number: 9514958
    Abstract: An etching method containing the step of processing a substrate having a first layer containing titanium nitride (TiN) and a second layer containing a transition metal by bringing an etching liquid into contact with the substrate and thereby removing the first layer, wherein the first layer has a surface oxygen content from 0.1 to 10% by mole, and wherein the etching liquid comprises an ammonia compound and an oxidizing agent, and has a pH of from 7 to 14.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: December 6, 2016
    Assignee: FUJIFILM Corporation
    Inventors: Yoshinori Nishiwaki, Tetsuya Kamimura, Tadashi Inaba, Atsushi Mizutani
  • Patent number: 9499721
    Abstract: A chemical-mechanical polishing composition includes colloidal silica abrasive particles dispersed in a liquid carrier. The colloidal silica abrasive particles include a nitrogen-containing or phosphorus-containing compound incorporated therein such that the particles have a positive charge. The composition may be used to polish a substrate including a silicon oxygen material such as TEOS.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: November 22, 2016
    Assignee: Cabot Microelectronics Corporation
    Inventors: Steven Grumbine, Jeffrey Dysard, Ernest Shen, Mary Cavanaugh
  • Patent number: 9502264
    Abstract: A method for removing oxide selective to a material comprising at least silicon and at least nitrogen is disclosed, the method comprising providing in a reactor a structure having a surface comprising a region, wherein said region comprises a material comprising at least silicon and at least nitrogen, providing on said structure an oxide layer overlying at least a part of said region, and removing said oxide layer selective to said material by etching, thereby exposing at least a part of said at least overlaid part of said region, wherein said etching is done only by providing an etchant gas comprising boron, whereby a voltage bias lower than 30 V is applied to the structure.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: November 22, 2016
    Assignee: IMEC VZW
    Inventors: Eddy Kunnen, Vasile Paraschiv
  • Patent number: 9492851
    Abstract: A selective removal of metal and its anion species that are detrimental to subsequent hydrothermal hydrocatalytic conversion from the biomass feed in a continuous or semi-continuous manner prior to carrying out catalytic hydrogenation/hydrogenolysis/hydrodeoxygenation of the biomass that does not reduce the effectiveness of the hydrothermal hydrocatalytic treatment while minimizing the amount of water used in the process is provided.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: November 15, 2016
    Assignee: Shell Oil Company
    Inventors: Joseph Broun Powell, Robert Edward Trepte, Juben Nemchand Chheda
  • Patent number: 9489099
    Abstract: Disclosed herein is a fabrication method of a plate pattern including preparing an object on which the plate pattern will be formed, disposing hybrid particles having a hybrid structure of organic and inorganic substances on one surface of the object into a single layer, etching at least the hybrid particles, forming the plate pattern on the surface of the object on which the hybrid particles are disposed, and removing the hybrid particles.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: November 8, 2016
    Assignee: LG Electronics Inc.
    Inventors: Hooyoung Song, Minwoo Lee
  • Patent number: 9478439
    Abstract: Embodiments of the invention provide a substrate etching method, which includes: a deposition operation for depositing a polymer on a side wall of a silicon groove, an etching operation for etching the side wall of the silicon groove, and repeating the deposition operation and the etching operation at least twice. In the process of completing all cycles of the etching operation, a chamber pressure of a reaction chamber is decreased from a preset highest pressure to a preset lowest pressure according to a preset rule. The substrate etching method, according to various embodiments of the invention, avoid the problem of damaging the side wall, thereby making the side wall smooth.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: October 25, 2016
    Assignee: BEIJING NMC CO., LTD.
    Inventor: Zhongwei Jiang
  • Patent number: 9468950
    Abstract: A selective removal of metal and its anion species that are detrimental to subsequent hydrothermal hydrocatalytic conversion from the biomass feed in a continuous or semi-continuous manner prior to carrying out catalytic hydrogenation/hydrogenolysis/hydrodeoxygenation of the biomass that does not reduce the effectiveness of the hydrothermal hydrocatalytic treatment while minimizing the amount of water used in the process is provided.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: October 18, 2016
    Assignee: Shell Oil Company
    Inventors: Joseph Broun Powell, Robert Edward Trepte, Juben Nemchand Chheda
  • Patent number: 9466500
    Abstract: An apparatus and use of the apparatus to form nanometer sized features on a workpiece includes a plurality of individually biasable tips, and each tip has a diameter on the scale or 10 nm or less. By moving the tips above the surface of a workpiece in the presence of reactants, features can be directly formed on the workpiece on a sub-micron size, below the resolution of current photolithography. The features may be etched into a workpiece, or formed thereover.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: October 11, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: James Francis Mack, Stephen Moffatt
  • Patent number: 9455135
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a hard mask on the gate structure and the ILD layer; forming a first patterned mask layer on the hard mask; using the first patterned mask layer to remove part of the hard mask for forming a patterned hard mask; and utilizing a gas to strip the first patterned mask layer while forming a protective layer on the patterned hard mask, wherein the gas is selected from the group consisting of N2 and O2.
    Type: Grant
    Filed: December 7, 2014
    Date of Patent: September 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, En-Chiuan Liou, Chieh-Te Chen
  • Patent number: 9455297
    Abstract: The invention relates to the field of semiconductor, more particularly, to a preparation process of image sensors, comprising: Step S1, providing a semiconductor structure, a top of which is provided with a groove, and leads being formed in said groove, the top of said semiconductor structure and an exposed surface of said groove are covered with a first dielectric layer; Step S2: depositing a second dielectric layer covering the upper surface of said first dielectric layer and said leads and filling said groove; Step S3: performing a reversed-etching process to thin said second dielectric layer, and to form a convex structure on a surface of said second dielectric layer above the groove; Step S4: performing a planarization process to said second dielectric layer to improve surface evenness of said second dielectric layer after grinding by the convex structure.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: September 27, 2016
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Siping Hu, Jifeng Zhu, Sheng'an Xiao, Jinwen Dong
  • Patent number: 9449845
    Abstract: Methods of etching exposed titanium nitride with respect to other materials on patterned heterogeneous structures are described, and may include a remote plasma etch formed from a fluorine-containing precursor. Precursor combinations including plasma effluents from the remote plasma are flowed into a substrate processing region to etch the patterned structures with high titanium nitride selectivity under a variety of operating conditions. The methods may be used to remove titanium nitride at faster rates than a variety of metal, nitride, and oxide compounds.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: September 20, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Jie Liu, Jingchun Zhang, Anchuan Wang, Nitin K. Ingle, Seung Park, Zhijun Chen, Ching-Mei Hsu
  • Patent number: 9437451
    Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a nitrogen-and-hydrogen-containing precursor. Reactants thereby produced etch the patterned heterogeneous structures with high silicon oxide selectivity while the substrate is at high temperature compared to typical Siconiā„¢ processes. The etch proceeds without producing residue on the substrate surface. The methods may be used to remove silicon oxide while removing little or no silicon, polysilicon, silicon nitride or titanium nitride.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: September 6, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Zhijun Chen, Jingchun Zhang, Ching-Mei Hsu, Seung Park, Anchuan Wang, Nitin K. Ingle
  • Patent number: 9437453
    Abstract: CMP selectivity, removal rate, and uniformity are controlled both locally and globally by altering electric charge at the wafer surface. Surface charge characterization is performed by an on-board metrology module. Based on a charge profile map, the wafer can be treated in an immersion bath to impart a more positive or negative charge overall, or to neutralize the entire wafer before the CMP operation is performed. If charge hot spots are detected on the wafer, a charge pencil can be used to neutralize localized areas. One type of charge pencil bears a tapered porous polymer tip that is placed in close proximity to the wafer surface. Films present on the wafer absorb ions from, or surrender ions to, the charge pencil tip, by electrostatic forces. The charge pencil can be incorporated into a CMP system to provide an in-situ treatment prior to the planarization step or the slurry removal step.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: September 6, 2016
    Assignee: STMicroelectronics, Inc.
    Inventor: John H. Zhang
  • Patent number: 9435038
    Abstract: An improved method of etching a metal substrate is described. After a mask layer is applied to the metal substrate, an ion implantation process is performed which implants ions, such as oxygen ions, into the exposed regions of the metal substrate. This implantation creates regions of metal oxide, which may be more susceptible to etching. Afterwards, the exposed regions of metal oxide are subjected to an etching process. This process may be through vaporization or may be a wet etch process. In some embodiments, the etchant is selected so that the metal oxide binds with the etchant to form a volatile compound, which stays in the vapor or gaseous state. This may reduce the unwanted deposition of the metal to other surfaces. These ion implantation and etching processes may be repeated a plurality of times to create a recessed feature of the desired depth.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: September 6, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Thomas Omstead, William Davis Lee, Tristan Ma
  • Patent number: 9437447
    Abstract: Techniques disclosed herein include increasing pattern density for creating high-resolution contact openings, slots, trenches, and other features. A conformal spacer is applied on a bi-layer or tri-layer mandrel (multi-layer) or other relief feature. The conformal spacer thus wraps around the mandrels and is also deposited on an underlying layer. A fill material is deposited to fill gaps or spaces between sidewall spacers. A CMP planarization step then removes substrate stack material down to a material interface of the bi-layer or tri-layer mandrel, with a middle or lower material of the mandrel being a CMP-stop material. This technique essentially cuts off or removes rounded features such as upper portions of sidewall spacers, thereby providing a spacer material with a planar top surface that can be uniformly etched and transferred to underlying layers.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: September 6, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Anton J. deVilliers
  • Patent number: 9431268
    Abstract: Methods for controlled isotropic etching of layers of silicon oxide and germanium oxide with atomic scale fidelity are provided. The methods make use of a reaction of anhydrous HF with an activated surface of an oxide, with an emphasis on removal of water generated in the reaction. In certain embodiments the oxide surface is first modified by adsorbing an OH-containing species (e.g., an alcohol) or by forming OH bonds using a hydrogen-containing plasma. The activated oxide is then etched by a separately introduced anhydrous HF, while the water generated in the reaction is removed from the surface of the substrate as the reaction proceeds, or at any time during or after the reaction. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where accurate removal of one or multiple atomic layers of material is desired.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: August 30, 2016
    Assignee: Lam Research Corporation
    Inventors: Thorsten Lill, Ivan L. Berry, III, Meihua Shen, Alan M. Schoepp, David J. Hemker
  • Patent number: 9425041
    Abstract: Methods for controlled isotropic etching of layers of silicon oxide and germanium oxide with atomic scale fidelity are provided. The methods make use of NO activation of an oxide surface. Once activated, a fluorine-containing gas or vapor etches the activated surface. Etching is self-limiting as once the activated surface is removed, etching stops since the fluorine species does not spontaneously react with the un-activated oxide surface. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where accurate removal of one or multiple atomic layers of material is desired.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: August 23, 2016
    Assignee: Lam Research Corporation
    Inventors: Ivan L. Berry, III, Pilyeon Park, Faisal Yaqoob