Abstract: A printed circuit board card adapted to fit into a slot and make electrical connections with cooperating terminals in the slot, the slot being disposed on the main circuit board of a personal computer system, the main circuit board including a CPU, memory, a 32-bit address bus with control signals associated therewith, and input/output circuitry. The slot is coupled to the 32-bit address bus, being substantially a NUBUS bus, and the slot includes distinct identification line means which provide the slot with an identification number (distinct number) in the computer system. The card includes a decoder means which is coupled to the slot to receive the identification number; the decoder means has memory reservation means which causes 256 megabytes of memory space to be reserved for the card in the slot, such that, where the slot number is X, the 256 megabytes of reserved memory space begins at location $X000 0000 and ends at locations $XFFF FFFF.

Abstract: A cache memory includes an address back-up register for storing the physical address of the data where errors are generated for backing up the address register, a data array address back-up register for storing data address of the data where errors are generated for backing up the data array address register, and a request code back-up register for storing a preceding request code at the time of the error generation. When an error is detected by the system controller, data is read from the main memory according to the back-up registers and the control register, EYCY register and PSEDO ACK register, of the system controller.

Abstract: A circuit providing a joystick interface to a computer. The circuit plugs into the cartridge slot of the computer and receives power from the computer. The circuit includes an analog interface circuit, a read only memory (ROM) containing both a machine language program to drive the analog interface circuit, and a machine language application program. The analog interface circuit includes an analog-to-digital converter, a clock circuit, and a decoder. The circuit of the present invention also includes a tri-state bus interface circuit to communicate the state of input switches to the computer.