Abstract: A signal processing system comprises a delta-sigma modulation unit supplied with an input analog signal for producing one-bit data as a result of a delta-sigma modulation, an arithmetic unit supplied with the output one-bit data of the delta-sigma modulation unit for applying a predetermined arithmetic operation thereon, an integration unit for integrating an output of the arithmetic unit to produce multiple-bit data as an output, a comparator unit supplied with the multiple-bit data from the integration unit at a first input port and multiple-bit reference data at a second input port for producing one-bit data as a result of comparison, a feedback unit supplied with the output of the comparator unit for producing the multiple-bit reference data based upon the one-bit data produced by the comparator unit such that said reference data predicts the multiple-bit data supplied to the first input port, and a digital-to-analog conversion unit supplied with said output one-bit data of the comparator unit for convert