Abstract: A memory controller with improved data reliability and a memory system including the same are provided, and an operating method of the memory controller includes, based on deterioration information indicating a location of a deterioration region in the plurality of blocks, with respect to data stored in a first block, copying user data of a RAID to a normal region other than the deterioration region of a second block; copying parity data of the RAID among the data stored in the first block to the deterioration region of the second block; and updating mapping information between data constituting one RAID and transmitting the mapping information to the memory device. The deterioration information includes information regarding one or more word lines at specific locations included in the deterioration region in the plurality of blocks.

Abstract: According to one embodiment, a memory system includes nonvolatile memory including a plurality of memory areas and a memory controller. A read operation includes a first operation of reading data from a memory cell array and a second operation of transmitting at least a part of the read data to the memory controller. The memory controller determines, when executing the read operation in a first memory area and a second memory area in parallel, priorities of the second operation in the first memory area and the second operation in the second memory area based on a result of comparison between (A) a first total time period of the read operation in the first memory area and (B) a second total time of the read operation in the second memory area.

Abstract: A storage device may include a storage comprising a plurality of dies each having a plurality of memory blocks, and configured to provide a default ZNS (Zoned NameSpace) size to a host device; and a controller configured to generate a ZNS by selecting one or more memory blocks corresponding to a required ZNS size from the plurality of dies to allocate the selected memory blocks to the ZNS in response to a ZNS generation request signal which includes the required ZNS size and is provided from the host device.

Abstract: Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.

Abstract: A data search method for a memory device is provided. The data search method includes: based on a recorded compression mode, vectoring a search data to generate a search data vector, and based on the recorded compression mode, compressing the search data and a plurality of objects in a database; setting a search condition; searching the objects of the database by the search data vector to determine whether the search data is matched with the objects of the database; and recording and outputting at least one matched object of the database, the at least one matched object matched with the search data.

Abstract: A logical-to-physical (L2P) table is maintained, wherein a plurality of sections of the L2P table is cached in a volatile memory device. A total dirty count for the L2P table is maintained, wherein the total dirty count reflects a total number of updates to the L2P table. Respective section dirty counts for the plurality of sections are maintained, wherein each respective section dirty count reflects a total number of updates to a corresponding section. It is determined that the total dirty count for the L2P table satisfies a threshold criterion. In response to determining that the total dirty count for the L2P table satisfies the threshold criterion, a first section of the plurality of sections is identified based on the respective section dirty counts. The first section of the L2P table is written to a non-volatile memory device.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.

Abstract: A client device includes at least one memory configured to be used at least in part as a shared cache in a distributed cache. A network interface of the client device is configured to communicate with one or more other devices on a network each configured to provide a respective shared cache for the distributed cache. A Non-Volatile Memory express (NVMe) controller of the client device receives a command from a processor to access data in the shared cache and executes a program to use data read from the shared cache or data to be written to the shared cache to perform at least one computational operation. In another aspect, data is accessed in the shared cache using a kernel and data read from the shared cache or data to be written to the shared cache is used to perform at least one computational operation by the kernel.

Abstract: Data employed in computations is processed so that during computations more of the data can be fit into or maintained in a smaller but higher speed memory than an original source of the data. More specifically, a sensitivity value is determined for various items of the data which reflect the number of bits in the data items that are not garbage bits, and only information in the data items that are indicated by the sensitivity value to not be garbage bits are necessarily effectively retained. At least the information that is not garbage bits and the corresponding associated sensitivity are packed together. The results of computations that are performed using the data items as at least one of the operands for the computation are associated with a sensitivity that is derived from the individual sensitivities of the operands used in the computation.

Abstract: A storage device includes a plurality of nonvolatile memories, each including a plurality of memory blocks and a controller configured to control the plurality of nonvolatile memories, in which the controller is configured to buffer data chunks received along with write commands from a host, is configured to determine a size of continuous data based on a start logical address and a chunk size of the data chunks, is configured to determine a striping number indicating a number of nonvolatile memory which is for distributing and storing the data chunks in sub-page units based on the size of continuous data, and is configured to provide the data chunks to one or more nonvolatile memories selected from among the plurality of nonvolatile memories based on the determined striping number and the one or more selected nonvolatile memories are configured to perform a programming operation on the data chunks in parallel.

Abstract: A method for discarding personal information comprises at least one among partial overwriting, SLC programming, and applying an erase pulse. The method for discarding personal information comprises a step for acquiring the program status of personal information-containing data of a memory block to be erased, generating data having a status that is equal to or higher than the program status corresponding to the personal information, and carrying out a partial overwriting operation on the personal information by using the generated data.

Abstract: A memory system includes a memory and a controller. The memory is configured to store a number of valid data in each of a plurality of logical blocks and a number of valid data for each of a plurality of banks in each of the logical blocks. The controller is configured to: select logical blocks of garbage collection target candidates based on the numbers of valid data in the logical blocks; calculate a maximum value among the numbers of valid data for the banks in each of the logical blocks of the garbage collection target candidates as a respective comparison value; and select one of the logical blocks of the garbage collection targets based on comparing the respective comparison values of the logical blocks of the garbage collection target candidates with each other.

Abstract: Methods, systems, and devices for event management for memory devices are described. A memory system may include a frontend (FE) queue and a backend (BE). Each queue may include an interface that can be operated in an interrupt mode or a polling mode based on certain metrics. For example, the interface associated with the FE queue may be operated in a polling mode or an interrupt mode based on whether a quantity of commands being executed on one or more memory devices of the memory system satisfies a threshold value. Additionally or alternatively, the interface associated with the BE queue may be operated in a polling mode or an interrupt mode based on whether a quantity of active logical block addresses (LBAs) associated with one or more operations being executed on one or more memory devices of the memory system satisfies a threshold value.

Abstract: According to certain aspects, a memory subsystem is coupled to a memory controller of a host computer system via an interface. The memory subsystem comprises dynamic random access memory elements and a memory subsystem controller. During a normal memory read or write operation, the memory subsystem controller is configured to receive address and command signals associated with the memory read or write operations and to control the dynamic random access memory elements in accordance with the address and command signals. The memory subsystem controller is further configured to output via the open drain output a parity error signal in response to a parity error having occurred during the memory read or write operation. During an initialization operation, the memory subsystem controller is configured to output via the open train output a signal related to one or more parts of initialization operation sequences.

Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.

Abstract: A control method for a multi-channel non-volatile memory is shown. When reading a read target on the non-volatile memory, the controller increases the read count of the monitored unit to which the read target belongs and, based on the read count, determines whether to move data of the monitored unit covering the read target to a safe space to deal with reading interference. The monitored unit is smaller than a cross-channel management unit in read-count group. The controller accesses a parallel accessing space of the non-volatile memory in parallel through all of the channels, and allocates the parallel accessing space based on the cross-channel management unit.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving data to be stored on the memory device, storing a first copy of the data in a first set of memory cells of the memory device, and storing a second copy of the data in a second set of memory cells of the memory device. The operations can also include reading the first copy of the data and determining whether a threshold voltage of a cell in the first set of memory cells is within an overlapping range of voltage distributions, and reading the second copy of the data and determining whether the threshold voltage of a cell in the second set of memory cells is within an overlapping range of voltage distributions. They can also include using the second copy of the data.

Abstract: Methods, systems, and devices for memory operations are described. Data for a set of commands associated with a barrier command may be written to a buffer. Based on a portion of the data to be flushed from the buffer, a determination may be made as to whether to update an indication of a last barrier command for which all of the associated data has been written to a memory device. Based on whether the indication of the last barrier command is updated, a flushing operation may be performed that transfers the portion of the data from the buffer to a memory device. During a recovery operation, the portion of the data stored in the memory device may be validated based on determining that the barrier command is associated with the portion of the data and on updating the indication of the last barrier command to indicate the barrier command.

Abstract: Disclosed is an operating method of a storage controller communicating with a host and memory regions, which includes receiving a write request for a first memory region of the memory regions from the host, determining the first memory region as unavailable, based on a status information set, generating redirection information indicating that a second memory region of the memory regions is selected instead of the first memory region, performing a write operation in the second memory region based on the redirection information, updating status information of the second memory region in the status information set based on the write operation, outputting redirection result information indicating that write data of the write request are processed in the second memory region, to the host, and receiving a read request corresponding to the write data and including information of the second memory region from the host.