Patents Examined by Margaret R. Wanbach
  • Patent number: 4837458
    Abstract: A flip-flop circuit which requires only a small drive power and which operates with small power consumption, and in which the on-off transition occurs reliably. The flip-flop circuit comprises MOS field effect transistors (abbreviated as MOSFET's) and resistors. A first MOSFET and a second MOSFET, to which control signals are applied, are commonly-connected at their sources to be connected at the sources to a voltage source supplying a power supply voltage sufficiently higher than a threshold voltage of a third MOSFET and a fourth MOSFET interconnected to each other. The interconnected third and fourth MOSFET's are connected at their gates to the drains of the first and second MOSFET's, respectively, and to the drains of the fourth and third MOSFET's through resistors, respectively. The third and fourth MOSFET's are common-connected at their sources. An output terminal is led out from the drains of the first and third MOSFET's.
    Type: Grant
    Filed: August 19, 1987
    Date of Patent: June 6, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Sigeyuki Kawahata, Yoshitaka Sugawara
  • Patent number: 4797584
    Abstract: The power-on reset circuit is adapted to automatically provide a voltage pulse as a positive supply voltage is applied.
    Type: Grant
    Filed: February 13, 1987
    Date of Patent: January 10, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Alberto Aguti, Maurizio Gaibotti, Vittorio Masina