Abstract: An output buffer device utilizes a PMOS transistor as a first pull-up element and an NMOS transistor as a second pull-up element. An output signal is used to control a feedback circuit. An output signal is switched from a low to high voltage by a trigger voltage. The first pull-up element switches to the second pull-up element to complete the voltage switching from low to high. The device combines the high speed of the first pull-up element and the low noise of the second pull-up element.

Abstract: A system for counting the number of objects of known thickness in a stack and identifying the objects by their color in which an ultrasonic sensor is mounted at a known distance from a reference point that defines the beginning of the stack. The ultrasonic sensor is operated to measure the round trip transit time of ultrasonic energy reflected back from the closest object in the stack and the number of objects in the stack is calculated on the basis of the known distance and the round trip transit time. A color sensor senses the color of at least one object in the stack to identify the object. In a casino application where the objects are chips of known monetary value, the value of the chips in the stack can be calculated.

Abstract: A method for identifying a principal tooth in a series of teeth extending along at least a portion of a periphery of a rotatable object includes the steps of rotating the rotatable object, setting a counter to a predetermined value, measuring a first tooth in the series of teeth to obtain a first measurement, adding a qualifying value to the measurement to obtain a qualification measurement, measuring a second tooth in the series of teeth to obtain a second measurement, comparing the second measurement to the qualification measurement, and identifying the second tooth as the principal tooth when the second measurement exceeds the qualification measurement.

Abstract: A Gray Code counter includes first translator logic, binary incrementing/decrementing logic, second translator logic, and a clocked storage device. The first translator logic receives at an input a Gray Code number, I.sub.gray ?n:0! which the first translator translates into a binary number, I.sub.bin ?n:0!. The binary incrementing/decrementing logic either increments or decrements the binary number I.sub.bin ?n:0! to produce an incremented/decremented binary number, Z.sub.bin ?n:0!. The second translator logic translates the incremented/decremented binary number Z.sub.bin ?n:0! into an incremented/decremented Gray Code number, Z.sub.gray ?n:0!. The clocked storage device stores the incremented/decremented Gray Code number, Z.sub.gray ?n:0!. The clocked storage device also feeds the incremented/decremented Gray Code number, Z.sub.gray ?n:0!, to the input of the first translator logic.

Abstract: A mechanism for automatically enabling and disabling clock signals includes a driver for providing a clock signal as an output, a gate coupled to the driver, and a sensing circuit coupled to both the output of the driver and to the gate. The sensing circuit provides a signal to the gate responsive to the output being in a first state. The gate then prevents the driver from driving the clock signal responsive to the signal from the sensing circuit. In one embodiment, a generator is coupled to the driver for providing a waveform to the driver. The driver then provides the clock signal based on this input waveform. Additionally, the gate is situated between the generator and the driver. The gate, based on the output of the sensing circuit, can then prevent the waveform from being provided to the driver.

Abstract: A non-integer frequency divider is provided that can perform switching of a frequency division ratio setting at high speed in order to improve the phase noise of frequency synthesizers and raise their response speeds. The frequency divider is a non-integer frequency divider that performs frequency division with frequency division ratios that contain decimal fraction, and includes a first frequency divider which can be set to a number of integer frequency division ratios; a second frequency divider (i.e., a shift register); a bit selector; a CA value generator; and a .SIGMA..DELTA. modulator. Non-integer frequency division is realized by switching the settings of the frequency division ratio and the period number of the frequency division output signal of the first frequency divider and the setting of the frequency division ratio of the second frequency divider.

Abstract: A counter operated on the 2-phase clock which divides a lag time occurring in shift circuits into two parts, one being on the basis of a first clock and the other being on the basis of a second clock, the lag time in each part being independently accumulated so as to diverge the lag time, thereby speeding up the operation of the counter.

Abstract: This invention relates to a programmable frequency divider that includes a plurality of flip-flops that are clocked at a frequency to be divided. The plurality of flip-flops is operatively arranged to allow the connection in a ring of a predetermined number of them, selected according to a desired frequency division ratio. In one embodiment, the smallest selectable ring includes at least two successive flip-flops that are initialized to a first state, immediately followed by at least two successive flip-flops that are initialized to the opposite state.

Abstract: Internal node timing on an integrated circuit which is supplied with a clock signal from a system clock, the cycle time of which can be varied is measured by connecting a sequential element such as a latch to the node to measured and clocking it with a delayed measurement clock while increasing the clock cycle time. The output of the sequential element is an output pin of said integrated circuit. The measurement clock has the same cycle time as the system clock but has a latching edge delayed, the delay being at least 1.5 times the nominal system clock cycle time when it is desired to make measurement over both the high phase and low phase. The output pin is observed and the clock cycle time at which the sequential element fails to latch the current value determined. In a further embodiment, two sequential elements are used to make two measurements of this type and the difference between the two measurements is used to compute the time delay between the two nodes being measured. One node may be a clock node.

Abstract: A rapid start-up voltage reference (8) is provided. The rapid start-up voltage reference (8) includes a voltage reference circuit (10) operable responsive to a shut-down signal ENABLE. The shut-down signal has an enable state and a disable state. The voltage reference circuit (10) has a feedback loop (12) which has a first node (NODE 1). The voltage reference circuit (10) is operable to produce an output reference voltage (V.sub.REF) when the shut-down signal is in the enable state. A rapid start-up circuit (14) is coupled to the first node (NODE 1) and to a power supply node (V.sub.cc). The rapid start-up circuit (14) includes a capacitor (16) and is operable responsive to the shut-down signal to charge the capacitor (16) when the shut-down signal is in the disable state and to connect the capacitor (16) to the first node (NODE 1) when the shut-down signal is in the enable state.

Abstract: An output driver is provided for operating in a primary power supply environment to drive an output system that can have voltages associated therewith that are higher than the primary power supply level. The driver includes a pull-down N-channel (34) and a pull-up P-channel transistor (44). An output node (40) is driven by the transistor (34) and (44). An N-channel protection device (38) is disposed between node (40) and transistor (34) and an N-channel transistor (48) is disposed between node (40) and transistor (44). Transistor (38) has the gate thereof biased to the primary supply voltage level and the transistor (48) has the gate thereof biased to a voltage slightly above the primary supply voltage level.

Abstract: A system rapidly dynamic values (B) on a bus (12) to a programmable but thereafter fixed reference value (C). The system includes first leads (33) coupled to a comparison means (35), second leads (13) coupled to the bus (12) and third leads (34, 36) coupled to sources of potential (GND, VCC) related to logical HIGH and LOW of the fixed reference value (C). The leads (33, 13, 34, 36) are coupled in one or more programmable connection cell (32). Connections (471) or disconnections (461) are made between the leads (33, 13, 34, 36) so that the dynamic values (B) and the appropriate logical HIGH and logical LOW values are presented to the correct inputs of the comparison means (35). The programmable connections cells (32) invert the reference value (C) to (C) for coupling to the comparator (35). The system replaces a level of conventional decode logic (16) by the programmable interconnections (47), thereby reducing delay time, using fewer devices and occupying less circuit area.

Abstract: A switching circuit utilizing MOS transistors without body effect having a first transistor inserted with source and drain terminals between two connection terminals, and a second and third transistors inserted in series by means of their respective source and drain terminals between the first transistor and a ground. The gate terminal of the second transistor is connected to the gate terminal of the first transistor to which is applied a command signal. Upon switching a signal is applied in phase opposition to the command signal to the gate terminal of the third transistor. The substrates of the first and the second transistors are connected to a connection node between the second and third transistors. The substrate of the third transistor is connected to ground.

Abstract: A multiple match detection circuit including an array of N and P-channel pull-up and pull-down devices receiving a corresponding array of hit line signals for developing complementary bit line signals, which are provided to the respective inputs of a differential comparator. Respective buffers drive the bit line signals to a maximum voltage differential in normal mode. For each hit line asserted, the pull-up and pull-down devices modify the voltage of the corresponding bit line voltage between the bit lines by an incremental amount, thereby decreasing the differential. Any single hit line does not cause enough of a voltage change to reverse the polarity of the differential voltage between the bit lines.

Abstract: A data shift control circuit for a shift register in response to a logic operation command code is disclosed. The shift register includes a first register and a second register and the logic operation command code includes a first portion and a second portion. The circuit includes a first decoder for decoding the first portion to transmit a move signal; a second decoder for decoding the second portion to transmit a control signal; a control signal channel, electrically connected to the first register and the second register, for allowing the first register and the second register to receive the control signal and for allowing the shift register to execute a first action; and a move signal channel, electrically connected to all registers of the shift register for allowing the all registers to receive the move signal and for allowing the move register to execute a second action.

Abstract: A bill counter comprises a case body formed to be a size which can be carried; a display section provided on the surface of the case body; an insertion port provided on one side of the case body which is capable of being expanded/contracted; a taking-out port provided on the other side of the case body; a first feeding-out device which is provided on the insertion port side within the case body and feeds out bills in a bundle inserted to the insertion port by a few sheets; a second feeding-out device which is provided on the taking-out port side within the case body and feeds out bills one by one fed out by the first feeding-out device; a driving section which drives simultaneously the first and the second feeding-out devices; an identifying sensor which identifies bills going toward the taking-out port; and a control section which outputs a signal displaying the number of sheets by unit of each bill and the total amount at least to said display section based on the signal from the identifying sensor and a si

Abstract: An improved CMOS current source circuit capable of constantly generating a certain reference voltage irrespective of an analog supplying voltage, a substrate temperature, and a temperature variation, which includes a start unit for driving the CMOS current source circuit in accordance with a start signal; a bias current generating unit driven by the start unit for generating a bias current in accordance with an analog voltage, a substrate voltage, and a temperature variation; a current input unit for inputting a bias current; and a current compensation unit for receiving a bias current through the current input unit and for compensating the bias current in accordance with an analog voltage, a substrate voltage, and a temperature variation and for generating a reference current.

Abstract: A CMOS current reference is provided that is relatively independent of supply voltage and generates a substantially steady current. The current reference includes a plurality of P-channel FETs and a plurality of zero threshold voltage N-channel FETs that provide a high level of voltage supply rejection at relatively low supply voltage levels (1.5 to 3.3 volts). Utilization of the P-channel FETs and the zero threshold voltage N-channel FETs in a current mirror and cascade configuration reduces the sensitivity of the current to variations in the supply voltage. The current reference exhibits higher offset voltage capabilities. In addition, the CMOS current reference may be designed to compensate for process variations since the current will increase as the channel length of the zero threshold voltage N-channel FETs increases.

Abstract: A chip (12) counter (10) employs an ultrasonic distance measuring system (40) to determine the number of chips in a stack (54, 56) in a chip tray (16) channel (14). A computer (32) initially stores an average chip thickness (T) and receives distance data from the ultrasonic distance measuring system indicative of a first distance (D.sub.1) to the bottom of an empty channel. To count chips, the computer repeatedly receives data from the ultrasonic distance measuring system indicative of a second distance (D.sub.2) to the top of the stack of chips in the channel. The computer subtracts the second distance from the first distance to determine a height of the stack of chips and then divides the height by the average chip thickness to provide a continuous count of the number of chips in the channel. In a multichannel chip tray, each channel has a distance measuring transducer, and a multiplexer (28) scans all the transducers to provide the computer with second distance data for all channels in the chip tray.

Abstract: A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.