Abstract: Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus (3) having latency intolerant modules connected thereto, a secondary bus (4) having latency tolerant modules connected thereto, and a primary to secondary bus interface module (5) interconnecting the primary and secondary buses.

Abstract: A computer being controlled is coupled via a communications bus to at least one other device comprising one or more authorized management devices. The one or more authorized management devices are coupled to a management port. Only management commands received from authorized management devices via the management port may be executed or otherwise responded to. Management commands received from other devices are ignored. In a preferred embodiment, the communication bus is an IEEE 1394 serial bus. In this manner, the present invention provides for the use of more direct communication technologies, such as the IEEE 394 serial bus, while simultaneously providing a greater degree of security than previously available.

Abstract: A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether any of the co-processors in the multiprocessor subsystem generated an interrupt. If one of the co-processors generated an interrupt, the ISR schedules the DPC for execution and disables sending of further interrupts from all of the co-processors. The DPC services pending interrupts from any of co-processors, then re-enables sending of interrupts from the co-processors.

Abstract: A bus bridge on a primary RAID controller receives user write data from a host and writes the data to its write cache and also broadcasts the data over a high speed link (e.g., PCI-Express) to a secondary RAID controller's bus bridge, which writes the data to its mirroring write cache. However, before writing the data, the second bus bridge automatically invalidates the cache buffers to which the data is to be written, which alleviates the primary controller's CPU from sending a message to the secondary controller's CPU to instruct it to invalidate the cache buffers. The secondary controller CPU programs its bus bridge at boot time with the base address of its mirrored write cache to enable it to detect that the cache buffer needs invalidating in response to the broadcast write, and with the base address of its directory that includes the cache buffer valid bits.

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: A smart card virtual hub combines an ISO7816 compliant smart card reader interface with a USB hub that provides one or more attachment points for connection of devices to the USB bus, thereby interfacing such devices to the host computer. The hub in the presently preferred embodiment of the invention provides one port to which one USB functional device, such as a keyboard, may be attached. The attached keyboard shares a common USB bus bandwidth with the internal embedded smart card reader through a host-scheduled, token-based communication protocol that is handled by the USB driver and the device driver.

Abstract: An information processing system operating in response to a remote control signal transmitted from a remote controller, the information processing system including a remote signal receiver to receive the remote control signal; an interrupt generator to generate a system management interrupt signal when receives the remote control signal by the remote signal receiver; and a controller to process the remote control signal received by the remote signal receiver and to control the information processing system to operate in correspondence to the remote control signal when the interrupt generator generates the system management interrupt signal.

Abstract: A method and system for routing network-based data arranged in frames is disclosed. A host processor analyzes transferred bursts of data and initiates an address and look up algorithm for dispatching the frame to a desired destination. A shared system memory existing between a network device, e.g., an HDLC controller, working in conjunction with the host processor, receives data, including any preselected address fields. The network device includes a plurality of ports. Each port includes a FIFO receive memory for receiving at least a first portion of a frame. The first portion of the frame includes data having the preselected address fields. A direct memory access unit transfers a burst of data from the FIFO receive memory to the shared system memory. A communications processor selects the amount of data to be transferred from the FIFO receive memory based on the desired address fields to be analyzed by the host processor.

Abstract: A system and method for transferring information in a multi-channel, point-to-point environment are described. In one embodiment, a number of processing chips are connected to a bridge bus. A bridge is connected to the bridge bus and to a system bus. In addition, a memory is connected to the bridge.

Abstract: Multiple memory channels of a multi-channel memory architecture are effectively bridged together to enable data traffic associated with various nodes in daisy chain arrangement to be communicated over both memory channels. For example, a daisy chain arrangement of nodes, such as FB-DIMM memory modules disposed in a first memory channel may be coupled to a second memory channel, with support for communicating data associated with one of the nodes over either or both of the first and second memory channels.

Abstract: A communication control circuit that performs the process of receiving a response to send data in synchronous transfer mode within a certain period of time without using an external control circuit. A permissible time calculation section calculates permissible time for receiving response data corresponding to send data sent to each of communication nodes connected to a serial bus from data length of the send data, data length of the response data, and a number of the communication nodes to which the send data is sent on the basis of communication cycles specified in the synchronous transfer mode. A response time management section determines whether the response data received as a response to the send data sent via the serial bus is received within the permissible time calculated by the permissible time calculation section. As a result, time taken to receive the response data corresponding to the send data is guaranteed.

Abstract: An interruption control system includes a PIC, an APIC and a power management unit disposed in a south bridge chip of a computer system. In response to the triggering of an interrupt status indicating signal received through an interrupt status indicating pin of a north bridge module or by the triggering of a peripheral device coupled to the south bridge chip, the PIC sends an interrupt signal to the CPU via an interrupt request signal pin when the computer system is in a PIC mode. The APIC is disabled when the computer system is in the PIC mode, and enabled when the computer system is in an APIC mode to generate a memory write cycle message to the CPU in response to the triggering of the peripheral device. The power management unit is optionally triggered with the interrupt signal or the interrupt status indicating signal to awake the CPU.

Abstract: Input devices and methods of operating the same are described. In one aspect, an apparatus includes a housing, a display screen, a main input device, a wireless receiver, a carrier bay, and an auxiliary input device. The main input device translates user manipulations of the main input device into control signals. The auxiliary input device is sized and arranged to be carried in and attached to the carrier bay in a docked state and detached from the carrier bay in an undocked state. In the undocked state, the auxiliary input device translates user manipulations of the auxiliary input device into control signals and wirelessly transmits the control signals for reception by the wireless receiver. In the docked state, the auxiliary input device is unresponsive to user manipulations of the auxiliary input device.

Abstract: A method of communicating between a first and a second processor includes the first processor sending a datum over a common control bus, and the second processor receiving the datum from the common control bus.

Abstract: An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an interrupt source interface operable to receive interrupt requests generated by a first plurality of interrupt sources, and a daisy chain interface operable to receive a daisy chain interrupt request output by a further interrupt controller based on a second plurality of interrupt requests generated by a second plurality of interrupt sources. The daisy chain interface includes a priority input operable to receive a daisy chain priority signal indicating a priority associated with the daisy chain interrupt request. Prioritization logic is operable to receive the daisy chain priority signal and to apply predetermined prioritisation criteria to determine the highest priority interrupt request selected from the daisy chain interrupt request and the interrupt request generated by the first plurality of interrupt sources.

Abstract: A system and method of automatically switching control of a bus in a processor-based device is provided. In a server, control of a bus is automatically switched from a controller mounted on the system board to a controller located on an optional expansion card upon connection of the expansion card to the system board. Automatic switching includes isolating the on-board controller from the bus and appropriately terminating any transmission line ends on the bus resulting from the establishment of the alternative control path.

Abstract: Data bus system and method are provided for controlling service engagements for bus users. At least one bus user provides services and other bus users use these services. A resource manager stores information about the available services and information about the service-providing bus users. The resource manager reserves a service from a providing bus user if the service can be used, and sends a response to a requesting bus user, allowing the requesting bus user to use the service from the providing bus user via the data bus. Information about the provided services is provided on the data bus via a standard interface by the bus users and a change in the provision of a service by a bus user is made available to the resource manager via the standard interface. The resource manager controls the service engagement on the basis of a priority information item.

Abstract: A system and method for guaranteeing transactional fairness among multiple requesters contending for a common resource in a cache-coherent multiprocessor system is described. Batch processing is used to control servicing of multiple requests made by multiple requesters (such as processors) of a common resource in a cache-coherent multiprocessor system. Specifically, identification numbers are assigned to requests as they are received from the multiple requesters. The identification numbers are then used in conjunction with batch processing to prioritize and guarantee servicing of the requests.

Abstract: An interrupt control device for issuing interrupts to a central processing unit (CPU) includes an object acquiring unit for acquiring data or resource(s) for use by the CPU and an interrupt issuing unit for issuing interrupts to the CPU. The interrupt issuing unit issues each interrupt to the CPU before the object acquiring unit actually acquires the data or the resource, but the interrupt indicates that the data or the resource is available. The interrupt control device further includes a use delay unit for delaying the use of the data or resource by the CPU unit until the object acquiring unit acquires the data or the resource if the CPU which has received the interrupt requests the use of the data or the resource before the object acquiring unit acquires the data or the resource. By adjusting the exact timing of the issuance of the interrupt according to the actual delays experienced by the CPU, the overall delays associated with interrupt handling are minimized.

Abstract: A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it interprets a predetermined bit in the header as an interrupt request flag, rather than as its standard function specified by the PCI-Express specification. If the flag is set, the PCI-Express controller interrupts the processor after storing the message in the payload at the specified memory location. In one embodiment, an unused upper address bit in the header is used as the interrupt request flag. Additionally, unused predetermined bits in the TLP header are used as a message tag to indicate one of a plurality of message buffers on the receiving RAID controller into which the message has been written. The PCI-Express controller sets a corresponding bit in a register to indicate which message buffer was written.