Abstract: A method and an apparatus for executing efficient and cost-effective Atomic Layer Deposition (ALD) at low temperatures are presented. ALD films such as oxides and nitrides are produced at low temperatures under controllable and mild oxidizing conditions over substrates and devices that are moisture- and oxygen-sensitive. ALD films, such as oxides, nitrides, semiconductors and metals, are efficiently and cost-effectively deposited from conventional metal precursors and activated nonmetal sources. Additionally, substrate preparation methods for optimized ALD are disclosed.
Abstract: A single crystalline aluminum nitride laminated substrate comprising a single crystalline ?-Al2O3 substrate such as a sapphire substrate, an aluminum oxynitride layer formed on the substrate and a single crystalline aluminum nitride film as the outermost layer, wherein the dislocation density in the single crystalline aluminum nitride is 108/cm2 or less. The above single crystalline aluminum nitride laminated substrate is formed by nitriding the substrate by heating in the presence of carbon, nitrogen and carbon monoxide. The above single crystalline aluminum nitride film has a law dislocation density, little lattice mismatching and excellent crystallinity. A Group III element nitride film having excellent luminous efficiency can be formed on this aluminum nitride film. The above laminated substrate is used in a base substrate for a Group III element nitride film, a light emitting device and a surface acoustic wave device.
Type:
Grant
Filed:
March 26, 2004
Date of Patent:
May 22, 2007
Assignee:
The Circle for the Promotion of Science and Engineering
Abstract: A process for the wet chemical treatment of semiconductor wafers, in which the semiconductor wafers are treated with treatment liquids, has the semiconductor wafers firstly treated with an aqueous HF solution, then treated with an aqueous O3 solution and finally treated with water or an aqueous HCl solution, these treatments forming a treatment sequence.
Type:
Grant
Filed:
October 22, 1999
Date of Patent:
February 6, 2007
Assignee:
Siltronic AG
Inventors:
Roland Brunner, Helmut Schwenk, Johann Zach
Abstract: A single crystal silicon ingot having a constant diameter portion that contains arsenic dopant atoms at a concentration which results in the silicon having a resistivity that is less than about 0.003 ?·cm.
Type:
Grant
Filed:
September 27, 2002
Date of Patent:
November 7, 2006
Assignee:
MEMC Electronic Materials, Inc.
Inventors:
Milind Kulkarni, Mohsen Banan, Christopher V. Luers
Abstract: This invention relates to a method for depositing III-V semiconductor layers on a non III-V substrate especially a sapphire, silicon or silicon oxide substrate, or another substrate containing silicon. According to said method, a III-V layer, especially a buffer layer, is deposited on the substrate or on a III-V germination layer, in a process chamber of a reactor containing gaseous starting materials. In order to reduce the defect density of the overgrowth, a masking layer consisting of essentially amorphous material is deposited directly on the III-V germination layer or directly on the substrate, said masking layer partially covering of approximately partially covering the germination layer. The masking layer can be a quasi-monolayer and can consist of various materials.
Abstract: A method for fabricating semiconductor devices with thin (e.g., submicron) and/or thick (e.g., between 1 micron and 100 microns thick) Group III nitride layers during a single epitaxial run is provided, the layers exhibiting sharp layer-to-layer interfaces. According to one aspect, an HVPE reactor is provided that includes one or more gas inlet tubes adjacent to the growth zone, thus allowing fine control of the delivery of reactive gases to the substrate surface. According to another aspect, an HVPE reactor is provided that includes at least one growth zone as well as a growth interruption zone. According to another aspect, an HVPE reactor is provided that includes extended growth sources such as slow growth rate gallium source with a reduced gallium surface area. According to another aspect, an HVPE reactor is provided that includes multiple sources of the same material, for example Mg, which can be used sequentially to prolong a growth cycle.
Type:
Grant
Filed:
July 18, 2003
Date of Patent:
October 18, 2005
Assignee:
Technologies and Devices, Inc.
Inventors:
Vladimir A. Dmitriev, Denis V. Tsvetkov, Aleksei Pechnikov, Yuri V. Melnik, Aleksandr Usikov, Oleg Kovalenkov