Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

Abstract: The present disclosure relates to a reconstituted wafer- and/or panel-level package comprising a glass substrate having a plurality of cavities. Each cavity is configured to hold a single IC chip. The reconstituted wafer- and/or panel-level package can be used in a fan-out wafer or panel level packaging process. The glass substrate can include at least two layers having different photosensitivities with one layer being sufficiently photosensitive to be capable of being photomachined to form the cavities.

Abstract: A method for forming a memory device that includes providing a free layer of an alloy of cobalt (Co), iron (Fe) and boron (B) overlying a reference layer; and forming metal layer comprising a boron (B) sink composition atop the free layer. Boron (B) may be diffused from the free layer to the metal layer comprising the boron sink composition. At least a portion of the metal layer including the boron (B) sink composition is removed. A metal oxide is formed atop the free layer. The free layer may be a crystalline cobalt and iron alloy. An interface between the metal oxide and free layer can provide perpendicular magnetic anisotropy character.

Abstract: Provided are a light-emitting device and a display apparatus. The light-emitting device includes: sub-pixels located on an array substrate, the sub-pixels each includes a first electrode and a second electrode that are disposed opposite to each other, and a quantum migrating layer between the first electrode and the second electrode. The quantum migrating layer includes a non-light-exiting region and a light-exiting region corresponding to a backlight source. Transparent charged particles and quantum dots, which can be driven by an electric field to migrate in the light-exiting region and the non-light-exiting region, are encapsulated in an accommodating cavity of the quantum migrating layer. When there are quantum dots gathered in the light-exiting region, the quantum dots are excited to emit light; when there is no quantum dot in the light-exiting region, the light emitted by the backlight source directly passes and exits through the light-exiting region.

Abstract: A method for manufacturing a MEMS device includes disposing at least one bonding portion having a smaller bonding area in a region where an airtight chamber will be formed, and disposing a metal getter on a bonding surface of the bonding portion. According to this structure, when substrates are bonded to define the airtight chamber, the metal getter is squeezed out of the bonding position due to the larger bonding pressure of the bonding portion with a smaller bonding area. Then, the metal getter is activated to absorb the moisture in the airtight chamber. According to the above process, no additional procedure is needed to remove the moisture in the airtight chamber. A MEMS device manufactured by the above manufacturing method is also disclosed.

Abstract: A method of manufacturing a semiconductor structure includes the following operations. A wafer includes a crystal orientation represented by a family of Miller indices comprising <lmn>, wherein l2+m2+n2=1. A first chip and a second chip are over the wafer. A first edge of the first chip and a second edge of the second chip are adjacent to each other. A boundary extending in a direction between the first edge and the second edge is formed. A first included angle between the first direction and the crystal orientation is greater than or equal to 0 degree and less than 45 degrees.

Abstract: A semiconductor device includes a string of transistors stacked along a vertical direction above a substrate of the semiconductor device. The string can include a first substring, a channel connector disposed above the first substring, and a second substring. The first substring includes a first channel structure having a first channel layer and a first gate dielectric structure that extend along the vertical direction. The second substring is stacked above the channel connector, and has a second channel structure that includes a second channel layer and a second gate dielectric structure that extend along the vertical direction. The channel connector, electrically coupling the first and the second channel layer, is disposed below the second gate dielectric structure to enable formation of a conductive path in a bottom region of the second channel layer. The bottom region is associated with a lowermost transistor in the second substring.

Abstract: Semiconductor devices include a stack of vertically arranged channel layers. A gate stack is formed above, between, and around the vertically arranged channel layers. Source and drain regions and source and drain conductive contacts are formed. Inner spacers are formed between the vertically arranged channel layers, each having an inner air gap and a recessed layer formed from a first dielectric material. Outer spacers are formed between the gate stack and the source and drain conductive contacts, each having a second dielectric material that is pinched off to form an outer air gap.

Abstract: A semiconductor light emitting device includes a light extraction layer having a light extraction surface. The light extraction layer includes: a plurality of cone-shaped parts formed in an array on the light extraction surface, and a plurality of granular parts formed both on a side part of the cone-shaped part and in a space between adjacent cone-shaped parts. A method of manufacturing the semiconductor light emitting device includes: forming a mask having an array pattern on the light extraction layer; and etching the mask and the light extraction layer from above the mask. The etching includes first dry-etching performed until an entirety of the mask is removed and second dry-etching performed to further dry-etch the light extraction layer after the mask is removed.

Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

Abstract: A semiconductor device, including a substrate, and a deposit layer and a semiconductor layer formed sequentially on the substrate. The semiconductor layer has selectively disposed therein a first region, a second region and a contact region. A gate electrode is disposed on the first region and the semiconductor layer via a gate insulating film. A source electrode is formed in contact with the contact region and the second region. A drain electrode is disposed on the back surface of the substrate. The source electrode has a first titanium (Ti) film, and a titanium nitride (TiN) film, a second Ti film, and a metal film containing aluminum (Al) sequentially formed on the first Ti film. The source electrode may further include another TiN film, on which the first Ti film is formed.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a capacitor comprises a crystalline polar layer comprising a base polar material substitutionally doped with a dopant. The base polar material comprises one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element of one of 4d series, 5d series, 4f series or 5f series that is different from the one or more metal elements, such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV.

Abstract: A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation.

Abstract: A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

Abstract: An electronic module includes a substrate that includes a first main surface and a second main surface, at least one first electronic component that includes electrodes on a mounting surface thereof on the substrate and that includes a hollow portion, at least one second electronic component that includes electrodes on a mounting surface thereof on the substrate and that includes no hollow portion, and a sealing resin. The at least one first electronic component is mounted on the first main surface of the substrate and sealed with the sealing resin. The at least one second electronic component is mounted on the second main surface of the substrate and is not sealed with the sealing resin.

Abstract: In a light emitting device, a columnar part includes a first semiconductor layer, a second semiconductor layer different in conductivity type from the first semiconductor layer, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer is disposed between the substrate and the light emitting layer, the light emitting layer includes a first layer, and a second layer larger in bandgap than the first layer, the first semiconductor layer has a facet plane, the first layer has a facet plane, the facet plane of the first semiconductor layer is provided with the first layer, and ?2>?1, in which ?1 is a tilt angle of the facet plane of the first semiconductor layer with respect to a surface of the substrate provided with the laminated structure, and ?2 is a tilt angle of the facet plane of the first layer provided to the facet plane of the first semiconductor layer with respect to the surface of the substrate.

Abstract: A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.

Abstract: This disclosure is directed to systems and methods for maskless gap integration in interconnects having one or more vias above one or more interconnect lines (for example, metal interconnect lines). In various embodiments, the systems and methods described in the disclosure may serve to reduce electrical shorting between adjacent vias in the interconnects. In one embodiment, a spacer layer may be provided to mask portions of an interlayer dielectric (ILD) in the interconnect. These masked portions of the ILD can protect regions between adjacent interconnect lines from electrical shorting during subsequent metal layer depositions in a fabrication sequence of the interconnects. Further, in various embodiments, the vias may enclose a gap (for example, an air gap) without the need for additional masking steps, for example, without the need for additional lithography steps.