Abstract: A display substrate, a preparation method thereof, and a display apparatus are provide. The display substrate includes: a base substrate, an active layer disposed on the base substrate, a first gate insulating layer disposed on the active layer, a first conductive layer disposed on the first gate insulating layer, and a second conductive layer disposed on the first conductive layer and electrically connected with the first conductive layer; an orthographic projection of the first conductive layer on the base substrate does not overlap with an orthographic projection of the active layer on the base substrate; the second conductive layer includes gates; orthographic projections of the gates on the base substrate and the orthographic projection of the active layer on the base substrate have an overlap area; and the display substrate further includes: at least one insulating layer located between the first conductive layer and the gates.

Abstract: A display substrate and a manufacturing method thereof, and a display device are disclosed. The display substrate includes a base substrate, a plurality of sub-pixels, at least one group of contact pads, and a first insulation layer. The base substrate includes a display region and a bonding region located at one side of the display region. At least one group of contact pads includes a plurality of contact pads, at least one of the plurality of contact pads includes a first contact pad metal layer and a second contact pad metal layer, the second contact pad metal layer covers an edge of the first contact pad metal layer. The first insulation layer is located in gaps between the plurality of contact pads and covers edges of the plurality of contact pads, and is configured to expose surfaces of the plurality of contact pads facing away from the base substrate.

Abstract: Provided are an array substrate and a manufacturing method of an array substrate and a display panel and device. The array substrate includes a pixel circuit. The pixel circuit includes a first transistor and a second transistor, the first transistor includes a first active layer, the second transistor includes a second active layer, and the first active layer and the second active layer both include silicon. The array substrate further includes a first-type inorganic layer and a second-type inorganic layer and a first via hole. The first via hole is located above the first active layer and at least penetrates through the second-type inorganic layer. Concentration of hydrogen ions in the first active layer is less than concentration of hydrogen ions in the second active layer.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a base structure. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching the channel structures. The semiconductor device structure further includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. In addition, the semiconductor device structure includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.

Abstract: A display substrate, a manufacturing method thereof and a display apparatus are provided. The display substrate includes a display region and a bezel region. The display region includes a plurality of sub-pixels, and the display region includes a main display region and a plurality of corner display regions. The corner display region includes a first display region and a second display region, a distance between a center point of the first display region and a center point of the main display region is smaller than a distance between a center point of the second display region and the center point of the main display region; and a structure of sub-pixels of the first display region is different from a structure of sub-pixels of the second display region.

Abstract: A semiconductor device with EMI shield and a fabricating method thereof are provided. In one embodiment, the semiconductor device includes EMI shield on all six surfaces of the semiconductor device without the use of a discrete EMI lid.

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

Abstract: The present application provides a mask assembly and a display device. The display device comprises a display area and at least one non-display area, the display area surrounding the non-display area; the display device further comprises a transitional-display area adjoining the non-display area as well as the display area, respectively, wherein both the display area and the transitional-display area are used to display static or dynamic images; a thickness of a first electrode in the transitional-display area is smaller than or equal to a thickness of the first electrode in the display area. The presence of the transitional-display area prevents incomplete display caused by incomplete coverage of the evaporation material in the display device, such as black-edged display formed in an area where a connection bridge is located, thereby improving the display integrity.

Abstract: A display device includes: a first substrate including a pixel area and a transmissive area; a thin-film transistor on the first substrate; a planarization layer on the thin-film transistor; a first light emitting electrode on the planarization layer; a bank covering a part of the first light emitting electrode; a light emitting layer on the first light emitting electrode; and a second light emitting electrode on the light emitting layer and the bank. The transmissive area includes a transmissive hole penetrating the bank and the planarization layer.

Abstract: A solid-state imaging device including a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked, a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked, and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. A first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate to each other does not include a coupling structure formed from the first substrate as a base over bonding surfaces of the first substrate and the second substrate.

Abstract: A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

Abstract: A semiconductor device includes a substrate having a first area and a second area and an active area limited by an isolation layer in the first area and the second area, a p-type gate electrode doped with p-type impurities and including a p-type lower gate layer and a p-type upper gate layer on the p-type lower gate layer with a first gate dielectric layer disposed between the active area and the p-type gate electrode in the first area, and an n-type gate electrode doped with n-type impurities and including an n-type lower gate layer and an n-type upper gate layer on the n-type lower gate layer with a second gate dielectric layer disposed between the active area and the n-type gate electrode in the second area.

Abstract: A display panel and a fabricating method thereof, and a displaying device. The display panel includes a substrate, a resistance reducing trace, an inter-layer-medium layer and a signal line. The substrate is divided into a plurality of sub-pixel regions and a pixel separating region. The resistance reducing trace is provided on the pixel separating region of the substrate. The inter-layer-medium layer is provided on the substrate, and the inter-layer-medium layer has an opening exposing the resistance reducing trace. The signal line is provided within the opening, the signal line is connected to the resistance reducing trace, the signal line is distributed in a column direction along the display panel, and in a row direction along the display panel, a width of the opening is greater than or equal to a width of the signal line.

Abstract: A display device comprises a substrate; a driving transistor including a first active layer and a switching transistor including a second active layer, the first active layer and the second active layer being disposed on the substrate; a first gate insulating layer disposed on the first active layer of the driving transistor and the second active layer of the switching transistor; first and second gate electrodes disposed on the first gate insulating layer to overlap the first active layer of the driving transistor and the second active layer of the switching transistor, respectively; a first interlayer insulating layer disposed on the first gate electrode and the second gate electrode; and a second interlayer insulating layer disposed on the first interlayer insulating layer to overlap the first active layer without overlapping the second active layer in a plan view.

Abstract: A manufacturing method of a display device includes providing a first organic layer in a display area and a non-display area, to cover a pixel electrode and a pad electrode, respectively, providing a first electrode of a light emitting element, in the display area, the first organic layer being between the pixel electrode and the first electrode, after forming the first electrode, removing a portion of the first organic layer which is in the non-display area, to expose the pad electrode from the first organic layer; and providing a light emitting layer of the light emitting element, corresponding to the first electrode.

Abstract: A display device includes: a first active pattern on a light blocking pattern; a second active pattern at a same layer as that of the first active pattern; a first insulating pattern on the first active pattern; a second insulating pattern on the first active pattern, the second insulating pattern being spaced from the first insulating pattern, and having a first contact hole exposing the first active pattern; a first gate electrode on the first insulating pattern; a second gate electrode at a same layer as that of the first gate electrode, and overlapping with the second active pattern; a first etch stopper on the second insulating pattern, and having a second contact hole connected to the first contact hole; and a first electrode on the first etch stopper, the first electrode contacting the light blocking pattern and the first active pattern through the first and second contact holes.

Abstract: An electronic device includes a first substrate, a plurality of light emitting elements each having a horizontal length and a vertical length which are less than or equal to about 10 micrometers (?m), each of the plurality of light emitting elements being disposed on the first substrate, a quantum dot color filter layer disposed on the plurality of light emitting elements, and a first overcoat layer between a plurality of light emitting elements and the quantum dot color filter layer. The quantum dot color filter layer includes a plurality of quantum dot color filters partitioned by a plurality of first partition walls so as to be overlapped with the plurality of light emitting elements, respectively.

Abstract: A method of manufacturing a display panel includes forming a circuit layer including a gate, a source, and a drain on a base substrate and forming a light emitting element layer on the circuit layer. The forming of the circuit layer includes sequentially forming a preliminary metal layer, a preliminary oxide layer comprising molybdenum and tantalum, and a preliminary capping layer which comprise a preliminary electrode layer, cleaning the preliminary electrode layer, forming a photoresist layer pattern on the preliminary electrode layer, etching the preliminary electrode layer, and removing the photoresist layer pattern. During the etching of the preliminary electrode layer, a ratio between a removal speed ER1 of the preliminary oxide layer and a removal speed ER2 of the preliminary metal layer satisfies Equation 1 to maintain a low reflection property 1?ER2/ER1?3.

Abstract: An apparatus includes a semiconductor-based substrate with a functional structure that is formed in or on the semiconductor-based substrate. The apparatus includes a frame structure surrounding the functional structure and includes a coating that covers the functional structure and is delimited by the frame structure.