Abstract: A flight simulator includes a central processing unit and a flight simulation environment controlled by the central processing unit for simulating the flight of an aircraft. The central processing unit is programmed to observe a full fidelity model of the aircraft in flight so as to extract pilot inputs and aircraft responses at each of successive time intervals. The central processing unit is further programmed to calculate a damping and an undamped natural frequency of the aircraft from the extracted pilot inputs and aircraft responses and to simulate the flight of the aircraft by applying the damping and undamped natural frequency to a second order transfer function.

Abstract: Predictive models have always been sought in the physical, biological and social sciences, but the application of such models may not produce reliable results. Before accepting a prediction from any model, it is essential to ascertain that the model is applicable to make the prediction. The present invention generally relates to a method for validating a model based prediction and more specifically, to a method for validating whether selected models are applicable to selected queries and comparing the performance of the predictive model on a query object or point, etc., with the performance of the predictive model on an existing object having a shortest property sensitive similarity index from the query object or point, etc. in a data processing system.

Abstract: A medical claims analysis system and method categorizes medical claims into episodes of care having predetermined diagnostic cluster types. The system analyzes medical claim items, some of which have principal diagnosis codes, and some of which have non-principal, missing, or incorrect diagnosis codes. Patient treatment episodes (PTEs) are formed from the principal diagnosis codes, each PTE being of a particular diagnostic cluster type. The system categorizes non-principal-diagnosis claim items into the PTEs on the basis of temporal, physiological or clinical relationships between the claim items and the PTEs. A drug lookup table enables drug claims to be properly categorized in the PTEs. A diagnostic cluster lookup table enables claim items to be categorized into PTEs with ongoing treatment windows for which the diagnosis code of the claim item is in the diagnostic cluster lookup table. The system merges PTEs of the same diagnostic cluster type when the treatment windows of the PTEs overlap.

Abstract: A signal processing circuit which provides an accurate, continuously tunable impedance includes a tunable continuous time transconductor G(s) which may, for example, be an opto-electronic inductor. This has a discrete time current processor-H(z) connected between its input and output so as to provide current feedback. The discrete time current processor may be based on a switched current memory which can be adapted to provide scaler, differentiator or integrator configurations.

Abstract: A method for modeling linear control systems that are asymptotically stable provided that any initial deviation is within a definite bound is described. The method includes the steps of generating a parametric model of the quasi steady state system, generating a time-invariant parametric mapping function, using the system model, to relate a system setpoint parameter at a system setpoint function to an input process parameter implicit in a system implicit parameter, and generating an interface protocol to adjust the time-invariant parametric mapping function to account for any time-dependent variations in the relative performance between the input process parameter and the implicit system parameter.

Abstract: An extremely high-speed, very stable system and a method for concurrent computing between heterogeneous simulators are shown, in which heterogeneous simulators for analyzing a complicated physical phenomenon are coupled based on a coupled equation thereby to obviate the disadvantages of the conventional noncoupled and coupled methods. A numerical calculation unit includes a calculation control unit equipped with an agent function having a heterogeneous coupling variational equation calculation unit, a convergence decision unit and a search vector setting unit. A parameter and a variable are supplied from the heterogeneous coupling variational equation calculation unit into and out of a simulator A, a simulator B and a heterogeneous coupled equation thereby to form the heterogeneous coupling variational equation 1 and thus to determine a globally consistent solution.

Abstract: An information display method by use of a card including an information display section which includes a reversible thermosensitive recording portion capable of recording information reversibly therein with application of heat thereto, comprises the steps of (1) storing first information in the information display section; (2) comparing the first information stored in the information display section with a reference information; (3) displaying a second information in the information display section, based on the comparison of the first information and said reference information, and repeating the steps (1) to (3) by updating the first information and the second information when further information is stored in the information display section.

Abstract: Disclosed is an ion implantation simulation method including calculating a particle scattering process of each of sample particles as a simulation target using a Monte Carlo method, determining that the particle has stopped when scattering calculation gives zero energy of the particle, continuously performing the scattering calculation when the energy is not 0. When the scattering calculation yields an energy of the particle that has decreased to .alpha. (0.ltoreq..alpha..ltoreq.1) times the energy value at the time of implantation, the particle Is divided into a predetermined number N (N is an integer) such that the weight of the particle after division becomes 1/N that before division. The scattering calculation and the particle division process is repeated until particles having non-zero energy values are divided the predetermined number of times M (M is an integer) counting from the first division, and consequently, the weight of the particle becomes 1/N.sup.

Abstract: A program data creating method and apparatus for use with programmable devices in a logic emulation system provides high-speed logic emulation of an LSI for logic and function verification. The logic data defining the logic circuits of the LSI is divided into a plurality of unit blocks in a layout analogous to the floor plan represented by floor plan information for the LSI. The unit blocks are allocated to the programmable devices automatically. The names of the signals defined within the design data regarding the LSI are made to correspond with the names of the signals in effect when the design data is deployed within the programmable devices, after optimization of the logic. This allows the program data for the programmable devices to be created and corrected using the signal names as set forth in the design data.

Abstract: To simulate a bus of a circuit, a number of virtual bus stubs ("VBSs") each post simulated bus signals as a single step and execution of the simulation system which includes such a VBS continues. As a subsequent, separate step, the VBS substantially immediately thereafter reaps a resolved simulated bus state. Synchronization in such a system is achieved by grouping into zones all VBSs which collectively represent the simulated state of a single bus. Each VBS has one of four states, namely, reap running, reap stopped, post running, post stopped. When a VBS posts, it is determined whether any other VBS of the same zone has yet to reap a previously resolved simulated bus state. If such a VBS exists, the posting VBS moves from reap running state to a post stopped state and execution of the simulation system containing the posting VBS is suspended until the last VBS of a zone reaps the previously resolved simulated bus state.

Abstract: A method (30) and apparatus (300) for characterizing the operation of an architectural system designed through a plurality of design tasks (102-112). The design tasks are associated with architectural design rules (114-124) that compare a mapping of the system to a set of rules which are indicative of an error-free system. Objects in the mapping that do not conform to the architectural rules are identified and can be displayed at multiple architectural levels through one or more editors (26-28) and modified without leaving the editors. The system is dynamically characterized by annotating an RTL component (step 153) and simulating the system over a range of simulation cycles. The annotated component (130) monitors states of the system for storing in an analysis database (24). States at selectable simulation cycles are displayed in different orders and at multiple architectural levels.

Abstract: A method and apparatus for providing overlay memory support for ball grid array (BGA) microprocessor packages. A emulator having an overlay memory and an emulator probe is provided. The emulator is connected via the emulator probe to a target printed circuit board (e.g., adapter card). This target board includes a local processor, a local memory, a memory controller, and a local processor bus that couples them together. The local processor, local processor bus, and memory controller are integrated into a BGA chip package. Typically, the local processor executes software programs stored in the local memory. Upon receipt of a first signal, the memory controller disables the local memory and allows the emulator to drive data from the overlay memory onto the local processor bus so that the local processor may execute software programs included in the overlay memory.

Abstract: A clock routing design method enables a routing design for each hierarchy while paying an attention to each layout hierarchy to which a branch of a clock signal system extends and considering a whole chip. In the clock routing design method, a clock signal line is routed between a plurality of receiver terminals over a plurality of layout hierarchies while considering an equal-delay branch point yielding equal delays of a clock signal at the receiver terminals, the clock signal line is then routed between the equal-delay branch point positioning between the plural receiver terminals and the driver terminal. The clock routing design method is applicable to a layout design of wire patterns, cell, etc. on LSIs, printed circuit boards and the like.

Abstract: A system and method for interfacing at least one ISA and/or PCI compliant device with a PCMCIA compliant device socket (124) on a host computer (122) is disclosed. Preferably included in the system are structures to carry out the functions of; interrupt translation between the PCMCIA port and the ISA devices; direct memory access translation between the PCMCIA port and the ISA devices; translation of bus address latch enable signal between the PCMCIA port and the ISA devices; translation between memory read and memory write signal of the PCMCIA port and a system memory read signal and a system memory write signal of the ISA devices: translation between the PCMCIA port and 8 bit ISA devices; providing a clock signal to the ISA devices; supplying power to the ISA devices; and translation of the timing between the PCMCIA port and the ISA devices.

Abstract: A schematic diagram (32) for a printed circuit board (34) is synthesized (20) from a physical design file (56) and a graphical symbol file (86). The printed circuit board (34) has a plurality of parts (36) at least one of which has a plurality of pins (38), those parts (36) and pins (38) being defined in the physical design file (56), from which physical attributes (60) are extracted (58). The finished schematic diagram (32) will include a plurality of symbols (40) at least one of which has a plurality of nodes (41), those symbols (40) and nodes (41) being contained in the graphical symbol file (86) from which graphical attributes (90) are extracted (88). These physical attributes (60) and graphical attributes (90) are integrated (26) along with operator determined position data (168) to produce schematic application page files (30). These schematic application page files (30) may then be processed by a schematic drawing program (156) to plot (158) the finished schematic diagram (32) on a visual medium.

Abstract: Virtual bus stubs, which can be distributed among constituent computers of a computer network, and a central resolver cooperate to simulate a bus which is connected between multiple circuit parts of a simulated circuit. With each simulated cycle of a clock of the bus, the resolver (i) collects data from the virtual bus stubs representing signals driven on the bus by one or more of the circuit parts, (ii) resolves the current simulated state of the bus from the collected data, and (iii) sends data representing the resolved current simulated state of the bus to the virtual bus stubs. As a result, the virtual bus stubs and the resolver collectively accurately simulate the bus connecting the circuit parts. Since each circuit part has access to the simulated state of the bus through a respective virtual bus stub, each circuit part has access to all information regarding the simulated state of simulated circuit which is necessary for the accurate simulation of each circuit part.

Abstract: A work flow system is disclosed which, when a work effort is divided into multiple work points for execution in each of domains (sections or departments in enterprises, government offices, or the like), permits easy work allocation to work points in another domain. Each domain has a public flow management section for storing a public flow which consists of its own work points which is made open to another domain and, when detecting a public flow consisting of work points that belong to another domain in a flow indicating work originating in it, sends identification information for that public flow to that domain. Upon receipt of identification information for a public flow consisting of work points that belong to it from another domain, each domain carries out the public flow.

Abstract: A configurable logic system programmed to model a logic design comprises an array of programmable logic modules each configured to perform a partition block of the logic design and a module interconnect providing connections between the modules. The interconnect enables transmission of global links between the partition blocks of the modules. The modules time division multiplex the global links, with a destination module then demultiplexing the global links allowing the links to pass through to another FPGA. The modules are configured to transmit individual ones of the global links at time intervals determined in response to a ready time of the individual links. The ready times of individual global links are determined in response to receipt of parent global links and signal propagation delays across the modules. A parent of a particular global link is a link that affects a logic value of the global link. The present invention allows computation and communication simultaneously.

Abstract: A method of forming a scale model for simulation of a seismic survey is disclosed. The model includes layers which are formed by way of stereolithography or similar methods, from a CAD data base; the precision of the formation of the layers allows for construction of the model without adhesives between all layers for structural integrity of the model, although adhesive or a wetting agent may be used, depending upon the desired simulation experiment. The model also includes molded layers which are poured, injected, or otherwise introduced in liquid form. The liquid may then be solidified, or may remain in liquid form, depending upon the survey. These molded layers may be made into the prefabricated layers where appropriate, or during the process of constructing the model. Simulation of the survey may be made by imparting acoustic energy thereinto and detecting the same.

Abstract: An adaptive method of providing electrical interconnections for a plurality of feed-through lines each having a respective end extending to at least one substrate surface includes generating an artwork representation for the electrical interconnections using specified feed-through line end positions on the at least one substrate surface. The at least one substrate surface may include a surface of a stack of substrates with at least two substrates having feed-through line ends facing a common direction. Actual positions of the at least two of the feed-through line ends are determined, and a scale factor is estimated using the determined actual positions. Actual positions of others of the feed-through line ends are estimated using the scale factor, and the artwork representation is modified to properly include electrical interconnections to ones of the feed-through line ends which are not in their specified positions.