Abstract: A data communication network includes a plurality of primary virtual bridges, interconnected by primary virtual connections so as to transmit and receive data packets over the network to and from edge devices connected thereto. One or more backup virtual bridges, each associated with at least one of the primary virtual bridges, are connected by at least one secondary virtual connection to at least another one of the primary virtual bridges, so that upon a failure of one of the primary virtual bridges with which it is associated, the backup virtual bridge transmits and receives the data packets over the network via the at least one secondary virtual connection in place of the at least one of the primary virtual bridges.

Abstract: A method for transmitting faults across networks operating with different protocols is disclosed. The method includes identifying a fault at a local node, mapping a fault indication bit into a carrier packet, and transmitting the fault indication over a network. The method further includes receiving an indication that the fault was received at a remote node.

Abstract: A method for checking the reset function of an embedded processor is described. First, a check is made to see if a reset “flag” is not set (202) before branching to execute the test routine that initiates the embedded processor's reset (206). The test program sets the flag (204) before initiating the reset. When the processor resets and executes the test program from the beginning again, it determines that the flag was set (202), and it does not execute the reset instructions again.

Abstract: A system and method for the reliable firmware update of a disk connected to a fibre channel loop fabric allows the specified filers and other predetermined system devices connected to the fabric to be made aware of a firmware download to the target disk without need of a system broadcast message, and while avoiding an alert or error condition such as those encountered through an FC-AL reset request. The target disk returns a special downloading firmware reject code embedded in a low-level protocol that remains operative during a firmware download. This reject code is recognized by an accessing system device as indicating that the disk is currently downloading updated firmware. In this manner, having recognized the code, the system device holds any I/O operations with respect to the target disk for a given delay time. Thus, the system device does not misinterpret the unavailability of the disk as a failure, leading to an unwanted system-wide FC-AL reset state.

Abstract: A computer program product is provided that is readable by a computing system and encoding a computer program of instructions. The computer program product includes a hardware protected region that is utilized to store a portion of a computer BIOS. The BIOS includes a compressed computer program for restoring at least a portion of the computer BIOS when uncompressed and executed. The computer program product also includes a non-hardware protected region that is utilized to store the remainder of the computer BIOS. The hardware protected region may include an uncompressed computer program that may be utilized to uncompress the compressed program. The hardware protected region may also include an uncompressed program for detecting and initializing one or more memory devices within the computer system. Methods and apparatus are also provided for creating and utilizing the contents of the computer program product.

Abstract: A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.

Abstract: Techniques are provided for verifying the integrity of data written onto a memory device under test. A pseudo random number generator generates data patterns based on a known ‘seed’ that includes a date and time. A data storage system writes the data patterns onto the memory device under test and a reference drive. The data storage system then reads the data patterns from the memory device under test and the reference drive. Alternatively, the seed value is stored in the second memory device instead of the data pattern, and subsequently, the data storage system reads the seed value from the second memory device and regenerates the data pattern. The expected data patterns from the reference drive are compared to the data read from the memory device under test to verify whether the data storage system is operating properly.

Abstract: The invention relates to a method for monitoring a microcontroller having at least one normal operating state and one state with a reduced power consumption and to a circuit configuration for carrying out the method. The method enables the functionality of the microcontroller to be monitored even in the state with the reduced power consumption. The method includes steps of: during the normal operating state, receiving a status signal having pulses from the microcontroller and resetting the microcontroller if the pulses are not received within a predefined time pattern; and during the state with the reduced power consumption, transmitting a wakeup signal having a sequence of pulses to the microcontroller, and resetting the microcontroller if there is no confirmation by the microcontroller within a predefined time interval after a pulse of the wakeup signal.

Abstract: Method and system for saving the state of integrated circuit chips upon failure. In one aspect of the invention, a system for saving the state of an integrated circuit includes a non-volatile memory and a state-saving controller coupled to the non-volatile memory and coupled to the integrated circuit, where the state-saving controller saves the state of the integrated circuit to the non-volatile memory when a failure occurs in the integrated circuit.

Abstract: Systems, methods, and computer readable media are provided for very fast failover of streaming media servers. Fast failover allows for better quality of service. If a first server that is streaming media to a customer fails, a second server can continue operations in its place. Single frame failover can be accomplished by simultaneously streaming a digital asset by a first server and a second server. The second server flags each frame of the asset for discard, and meanwhile monitors the first server to ensure the first server is operational. Upon detecting a failure in the first server, the second server stops flagging frames for discard.

Abstract: A method, system and computer program for a computer message storage system such as electronic mail. This involves instancing a software archiver to relocate messages according to age and instancing a software backup subsystem to backup storage groups, to maintain a patch file and to copy to a backup file.

Abstract: A file server has plural NAS nodes having three processors dispersed in function, a shared cache memory shared between the plural NAS nodes and backed up by a battery, and plural storage devices. A log area for storing data with respect to an access request received by each NAS node is arranged in the shared cache memory. A network processor stores the data with respect to the access request to the log area, and transfers the data of the memory by a DMA at a reading time. Even when a failure is happened in a certain NAS node, another NAS node restores a file system using the log and continues processing to store the data with respect to the access request to the shared cache memory.

Abstract: A disaster recovery system with sequenced cascaded resynchronization comprises a plurality of data centers and a distributed control system. The individual data centers comprise a communication interface, a data storage, and a controller. The distributed control system is distributed and executable in the controllers of the plurality of data centers, and is capable of coordinating operations via the communication interfaces of the plurality of data centers to resynchronize a plurality of communication links between data center pairs of the plurality of data centers. The communication links including at least one synchronous link and at least one asynchronous link.

Abstract: A system and method for a processor thread acting as a system service provider is presented. A computer system boots up and initiates a service thread. The service thread is responsible for service related tasks, such as ECC checks and hardware log error checks. The service provider invokes a second thread which is used as an operational thread. The operational thread loads an operating system, a kernel, and runs various applications. While the operational thread executes, the service thread monitors the operational thread for proper functionality as well as monitoring service events. When the service thread detects a problem with either one of the service events or the operational thread, the service thread may choose to store operational data corresponding to the operational thread and terminates the operational thread.

Abstract: In a load testing apparatus, before the load test, three processor elements are combined, without overage or shortage, with a source processor element and a destination processor element as one pair, and the transmission time between the processor elements for each pair is measured. During the load test, packets are sent at a time from the source processor element to the corresponding destination processor element in the same pair, and the transmission time for each pair is measured. The transmission time measured for each pair in the load test is compared with a corresponding expected value data so as to evaluate the performance.

Abstract: A check system and method for checking EDC of a DVD sector without prior descrambling the sector. In the EDC check method, after the sector is received, a check value corresponding to a sector identification (ID) of the sector is generated. Meanwhile, an EDC value of the sector is calculated directly without prior descrambling the sector. Finally, the EDC value and the check value are compared. If the EDC value equals to the check value, a sector-correct signal is outputted; otherwise, a sector-error signal is outputted. Because the EDC check method and system of the invention skip the prior data descrambling step, the processing speed can be improved and the hardware resources may be more-efficiently used.

Abstract: A system includes a data processing core coupled to a system memory employing error correction code (ECC) circuitry. The core includes an indicator of when a correctable system memory error occurs and what address is associated with the error. A watchdog timer is instantiated on a system management device. Periodically, the timer prompts the management device to interrupt the processor and poll the error indicator to determine if a memory error has been detected. If an error is detected, the corresponding physical memory address is recorded. If a predetermined number of consecutive errors associated with a single memory address or range of addresses occurs, an alert is issued. In one embodiment, polling the error indicator is infrequent initially. As additional errors are detected, the polling frequency increases. At higher polling frequencies, the system may require a greater number of consecutive errors before taking additional action.

Abstract: A monitoring system includes a data input/output device, a processing device, a memory device and a transmission device. The data input/output device is coupled electrically to a host and a managing system for handling data transmission therebetween. The processing device is used to verify data that is transmitted to the data input/output device. The memory device is used to store the data verified by the processing device therein. The transmission device is adapted to establish a network connection with the managing system, and is operable so as to selectively route the data verified by the processing device to the network connection for reception by the managing system. A method for monitoring and processing screen data transmitted between a host and a managing system is also disclosed.

Abstract: A failure detection method enabling the detection of I/O bus failure and address parity error when installing I/O controllers connected to a system bus in a computer system, and also enabling failure location when installing units in slave/master relationships (e.g. SCSI controller and disk storage units) and when installing an additional slave in a computer system, thus improving the reliability of the system. The failure detection method comprises the steps of executing an instruction which involves providing I/O bus access to a memory to be used by an I/O controller after installed, determining that there is no failure when predetermined results are obtained with the instruction, and installing the I/O controller in the system.

Abstract: The invention provides a method and computer-readable medium for generically reporting the occurrence of an event occurring within a computer system. When an event occurs, parameter values corresponding to one or more predefined parameters that describe the event are identified. The parameter values are then stored in a normalized database configured for storing event parameters corresponding to the occurrence of an unlimited number of event types.