Abstract: A method of manufacturing the semiconductor device comprises elements described below;(a) forming a wiring pattern on an insulating film on a semiconductor substrate,(b) forming a reflow SiO.sub.2 film having a reflow shape by introducing SiH.sub.4 gas and H.sub.2 O.sub.2 gas into a reaction chamber which accommodates said semiconductor substrate and mutually reacting the SiH.sub.4 and H.sub.2 O.sub.2 gases in a temperature range of about -10.degree. C. to about +10.degree. C. in a vacuum of about 665 Pa or below,(c) plasma treating a surface of said reflow SiO.sub.2 film by introducing a gas including fluorine into said reaction chamber and discharging plasma in said reaction chamber, and(d) heat treating said semiconductor substrate.

Abstract: A method of supplying an excited oxygen, which comprises the steps of exciting a oxygen gas or a gas containing an oxygen atoms with plasma in a plasma discharge zone thereby forming an excited oxygen, and transferring a gas containing the excited oxygen into a reaction zone disposed next to the plasma discharge zone while keeping a pressure within the plasma discharge zone lower than that of the reaction zone. In a reaction chamber, a reaction by the excited oxygen is effected. As a result, the formation of a thin film on a substrate disposed in a reaction chamber, the etching of the substrate and the cleaning of the interior of the reaction chamber can be carried out.

Abstract: The reduction of surface recombination is required for the manufacture of electronic devices made of silicon as well as for the application of various measurements and analytical methods for determining the purity of silicon. According to this invention, a process will be described for applying a laquer layer to the surface of silicon wafers, wherby the surface recombination velocity will be reduced to a value below 100 cm/s.

Abstract: A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a highest etching/depositing component ratio and thus the lowest CMP removal rate; (c) forming a third HDP-CVD layer on the second HDP-CVD layer using the same HDP-CVD process but with a third HDP-CVD composition having a low etching/depositing component ratio and thus a high CMP removal rate; and (d) using a chemical mechanical process to remove at least a part of the third HDP-CVD layer using the second HDP-CVD layer as a stopper.

Abstract: A method of forming a silicon oxynitride (SiO.sub.x N.sub.y) passivation layer on a first side of a silicon wafer that has a plurality of parallel spaced conductive runners positioned thereon. The method comprises the steps of mixing TEOS, Oxygen, Nitrogen and either Ammonia or Diethyl amine and then introducing the mixture into a plasma deposition chamber containing the wafers that are to receive the passivation layer. The mixture is then energized into a plasma which results in a silicon oxynitride passivation layer being deposited onto the upper surface of the silicon wafer. Due to the characteristics of the TEOS gas, the passivation layer is very conformal which reduces the formation of keyholes in the passivation layer.

Abstract: A sequence of process steps forms a fluorinated silicon glass (FSG) layer on a substrate. This layer is much less likely to form a haze or bubbles in the layer, and is less likely to desorb water vapor during subsequent processing steps than other FSG layers. An undoped silicon glass (USG) liner protects the substrate from corrosive attack. The USG liner and FSG layers are deposited on a relatively hot wafer surface and can fill trenches on the substrate as narrow as 0.8 .mu.m with an aspect ratio of up to 4.5:1.

Abstract: A method useful in the backside processing of semiconductor wafers includes providing a semiconductor wafer having a first surface that has been substantially processed. The processed first surface of the semiconductor wafer is bonded to a handle wafer. Once bonded to the handle wafer, backside processing may be performed on the wafer. Following backside processing, the wafer is sawn while still bonded to the handle wafer. The individual dice are then removed from the handle wafer. This process involves fewer handling steps of the semiconductor wafer and the handle wafer provides support to the semiconductor wafer during backside processing thereby reducing opportunities for breakage.

Abstract: A semiconductor processing method of promoting adhesion of photoresist to an outer substrate layer predominately comprising silicon nitride includes, a) providing a substrate; b) providing an outer layer of Si.sub.3 N.sub.4 outwardly of the substrate, the outer Si.sub.3 N.sub.4 layer having an outer surface; c) covering the outer Si.sub.3 N.sub.4 surface with a discrete photoresist adhesion layer; and d) depositing a layer of photoresist over the outer Si.sub.3 N.sub.4 surface having the intermediate discrete adhesion layer thereover, the photoresist adhering to the Si.sub.3 N.sub.4 layer with a greater degree of adhesion than would otherwise occur if the intermediate discrete adhesion layer were not present. Further, a method in accordance with the invention includes, i) providing an outer layer of Si.sub.3 N.sub.4 outwardly of the substrate, the outer Si.sub.3 N.sub.4 layer having an outer surface; ii) transforming the outer Si.sub.3 N.sub.

Abstract: In a PECVD process, the plasma potential is controlled and maintained at a uniform level to confine the formed plasma to the gap area between the electrodes away from the influence of the walls of the discharge chamber. The plasma potential is controlled by operating the system at a high pressure, above about 12 Torr, and monitoring the operation by observing the DC bias on the upper or driven electrode until a positive potential, preferably greater than about 10V, is developed. At this point a symmetrical glow discharge and a controlled plasma exists between the driven electrode and the susceptor electrode, controllable by maintaining the pressure between about 14 and 20 Torr, to reduce plasma damage to the semiconductor body being coated which maximizes yield.

Abstract: An improved method for sharpening emitter sites for cold cathode field emission displays (FEDs) includes the steps of: forming a projection on a baseplate; growing an oxide layer on the projection using a low temperature oxidation process; and then stripping the oxide layer. Preferred low temperature oxidation processes include: wet bath anodic oxidation, plasma assisted oxidation and high pressure oxidation. These low temperature oxidation processes grow an oxide film using a consumptive process in which oxygen reacts with a material of the projection. This permits emitter sites to be fabricated with less distortion and grain boundary formation than emitter sites formed with thermal oxidation. As an example, emitter sites can be formed of amorphous silicon. In addition, low temperature materials such as glass can be used in fabricating baseplates without the introduction of high temperature softening and stress.

Abstract: A low dielectric constant (k) polymer is used for an interlayer dielectric (28) of a semiconductor device (20). Unlike prior art low k polymer materials, a photoresist layer can be deposted directly on interlayer dielectric (28) due to the presence of an in-situ glass layer (32) formed within the interlayer dielectric. Glass layer (32) is formed by silylating the upper surface of the polymer material and then oxygenating the upper surface, for example in a plasma environment in an oxygen atmosphere. Silylation can occur, for example, by implantation, vapor phase diffusion, or liquid phase diffusion of silicon into the upper surface of the polymer. The silylation and oxygenation processes are performed at low temperature and are thus compatible with use of organic polymer films.

Abstract: A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a lower etching/depositing component ratio and thus a higher CMP removal rate; and (c) using a chemical mechanical process to remove at least a part of the second HDP-CVD layer using the first HDP-CVD layer as a stopper. A protective layer with the same etching/deposition components but a different ratio than the sacrificial layer can be deposited on the sacrificial layer to minimize the dishing effect during the initial stage of the chemical mechanical polishing process.

Abstract: Antireflective layers (54, 86, and 109) have been developed that have discrete portions (541, 542, 861, 862, 863, 1091, and 1092). The discrete portions (541, 542, 861, 862, 863, 1091, and 1092) allow the antireflective layers (54, 86, and 109) to be used in many instances where using a single layer of uniform composition would be difficult or impossible. Alternatively, a single antireflective layer with a continuously graded composition can be used.

Abstract: A method for filling a trench in a semiconductor wafer that is disposed in a plasma-enhanced chemical vapor deposition chamber. The method includes the step of depositing a protection layer of silicon dioxide over the wafer and into the trench while the wafer is biased at a first RF bias level. The protection layer has a thickness that is insufficient to completely fill the trench. Further, there is provided the step of forming a trench-fill layer of silicon dioxide over the protection layer and into the trench while the wafer is biased at a second RF bias level that is higher than the first bias level.

Abstract: A new method of forming the dielectric layer of an integrated circuit using metal layout is described. An insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. Metal lines are formed overlying the insulating layer wherein the metal line mask is modified so that narrow trenches with constant width and depth are etched surrounding the metal lines and the remaining metal areas are not etched away but are left as dummy metal areas. The dummy metal areas are also etched into island pieces with size similar to the feature size. Narrow trenches with the same constant width and depth surround the dummy metal islands. A dielectric layer is deposited over the metal lines and dummy metal islands wherein voids are formed within the trenches between metal lines and wherein the top surface of the dielectric layer is planarized. The voids act to release system stress and to lower capacitance between the metal lines.

Abstract: A method is provided for forming silicon nitride stacks. A semiconductor substrate is cleaned to remove any native oxide, and an insulative material is disposed thereon. A plurality of films are deposited superjacent the insulative material, and each of the plurality of films converted into a dielectric to form a multi-layered stack. A fill layer is formed superjacent the multi-layered stack to seal any pinholes. The fill layer is formed by at least one of low temperature chemical vapor deposition (CVD) of oxide, low temperature deposition of nitride, low temperature re-oxidation of ozone, the low temperature is at least 20.degree. C.

Abstract: A graded gap fill process in which, in a high density plasma processing chamber, an insulating layer is deposited on a substrate without causing plasma charge-related damage to the substrate. The insulating layer is disposed above a first layer having trenches formed therein and below a subsequently deposited second layer. A protection layer is first deposited above the first layer using a first set of deposition parameters. This protection layer coats a surface of the first layer in a substantially conformal manner without forming voids in the trenches. A fill layer is then deposited above the protection layer using a second set of deposition parameters. The first set of deposition parameters is selected to reduce plasma charge-related damage relative to the second set of deposition parameters. The combination of the protection layer and the fill layer sufficiently electrically isolates the first layer from the second layer.

Abstract: A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.

Abstract: A polishing process for polysilicon gate patterning improvement using standard patterning techniques in the manufacture of high performance metal oxide semiconductor (MOS) devices. The addition of a short silicon polish step, after deposition and before patterning of a polysilicon layer reduces the non-planarity normally associated with polysilicon. Polysilicon polishing removes the surface roughness in the polysilicon layer caused by the grain structure of polysilicon and the surface roughness due to the replication of the underlying topography of the isolation and substrate regions. The described method for removal of both types of surface roughness leaves the polysilicon layer planarized without increasing the defect level already associated with the manufacture of high performance MOS devices.

Abstract: A reduced pressure device the reduced pressure chamber of which is constructed of stainless steel, and includes a passivation film formed on the exposed interior surface thereof. The film has a thickness of more than 50 .ANG. and is composed of two or more layers. One layer contains mainly chrome oxide formed in the vicinity of the interface of the stainless steel and the passivation film. The other layer contains mainly iron oxide formed in the vicinity of the surface of the passivation film. A passivation film may also be used with a thickness of more than 50 .ANG. and containing mainly a mixture of chrome oxide and iron oxide. Lastly a passivation film may also be used with thickness of more than 50 .ANG. and containing mainly chrome oxide.