Patents Examined by McDievnel Marc
  • Patent number: 6567723
    Abstract: A method, system and program processing unit for a robot, by which the safety during execution of a program is improved. The program processing unit comprises a program interpreter, a command rejection device and a command execution device. When the program interpreter sends a command in a program to the command rejection device, the command rejection device searches a command rejection rule storage section for a command rejection rule corresponding to the command, and if the rule is detected, retlieves input values from one or more sensors and the source information of the program from a source information storage section, judges command rejection conditions included in the rule based on the sensor information, source information, the command and its parameters, dismisses the command when the conditions are met, and sends the command to the command execution device when the conditions are not met.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: May 20, 2003
    Assignee: NEC Corporation
    Inventor: Tomoyoshi Sugawara
  • Patent number: 6453212
    Abstract: In a method for mobile robot motion control for the sake of controlling motional characteristics of the mobile robot, such motional characteristics of mobile robot are made to be virtually equivalent motional characteristics of a caster, whereby motional performance adaptable to an external force is realized. Thus, a method for mobile robot motion control by which an object can be cooperatively manipulated by human being and mobile robot is provided.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: September 17, 2002
    Assignee: Riken
    Inventors: Hajime Asama, Hayoto Kaetsu, Kuniaki Kawabata, Kazuhiro Kosuge, Yasuhisa Hirata
  • Patent number: 6226559
    Abstract: The mailing machine includes a microcontroller system for executing machine control algorithms during each control cycle and user interface algorithms. Each control cycle is divided into first discrete time intervals sufficient to allow completion of the respective control algorithms, and a second time interval for execution of user interface algorithm and, if required, completion of the user interface algorithm during subsequent control cycles.
    Type: Grant
    Filed: December 14, 1995
    Date of Patent: May 1, 2001
    Assignee: Pitney Bowes Inc.
    Inventors: Benita J. Felmus, Christopher S. Riello, Edilberto I. Salazar
  • Patent number: 6073059
    Abstract: A method of storing data in an internal storage device included in a process controller for controlling a molding machine divides storage areas of the internal storage device hierarchically into a molding condition data storage area for storing molding condition data specific to a product or an operating environment, a changeable machine data storage area for storing changeable machine data specific to the molding machine and necessary for setting operating conditions and subject to change when necessary, and an unchangeable machine data storage area for storing unchangeable machine data specific to the molding machine. The molding condition data storage area, the changeable machine data storage area, and the unchangeable machine data storage area can selectively be initialized individually or in an optional combination.
    Type: Grant
    Filed: March 7, 1997
    Date of Patent: June 6, 2000
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventors: Shoji Hayashi, Kiyoshi Sasaki
  • Patent number: 6026429
    Abstract: A mechanism for seanilessly searching and accessing information available through the Internet and other resources is disclosed. The present invention maintains a database of file objects available from numerous sources. The present invention updates the database periodically to ensure the accuracy and completeness of it. The present invention also may access and retrieve data from numerous sources when prompted by a sige and simple command initiated by the user. The user is shielded from the quirks and intricacies of various information sources.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: February 15, 2000
    Assignee: America Online, Inc.
    Inventors: David R. Jones, Gregory S. Gerard, Julie H. Hanley
  • Patent number: 6004022
    Abstract: A product sum operation apparatus in which an increase in the circuit scale of the product sum operation apparatus can be suppressed and the operation speed can be increased even when the number of bits to be operated is increased. A partial product generating circuit has a partial product operation circuit of 12 bits.times.24 bits structure. A multiplier is divided into a lower digit multiplier of lower 12 bits and an upper digit multiplier of upper 12 bits. The partial product generating circuit receives sequential outputs from each of the lower digit multiplier and upper digit multiplier to generate corresponding lower digit partial products and upper digit partial products. An adder circuit adds the lower digit partial products, and the results of addition are temporarily held in a register of 48 bits structure.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: December 21, 1999
    Assignee: NEC Corporation
    Inventor: Masahiro Tsubakihara
  • Patent number: 5949799
    Abstract: A data mover which provides guaranteed transfer of data between two locations. The data mover includes a pair of data packet memories for input, a pair of data packet memories for output, and a controller which alternately switches each of the paired data packet memories between a data loading mode and a data unloading mode. The controller enables one of the paired data packet memories in the data loading mode and enables the other one of the paired data packet memories in the data unloading mode. The controller switches the modes of the paired data packet memories upon receiving an acknowledgement of moved data.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: September 7, 1999
    Assignee: Cypress Semiconductor Corp.
    Inventors: Edward L. Grivna, Paul Scott
  • Patent number: 5910959
    Abstract: A methodology for a modem control channel is disclosed. The channel allows faster seamless rate change and precoder tap exchange than the baseline procedure for seamless rate change, allowing for more robust transmission of control information. It can also be use to convey side-information in the case of multiple data applications, serving the purpose of mode switching. Thus, with a single control channel both the needs for seamless rate change and transmitting control information for multiple data applications can be met.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: June 8, 1999
    Assignee: Conexant Systems, Inc.
    Inventors: Sverrir Olafsson, Sandeep Rajpal
  • Patent number: 5862159
    Abstract: A method for encoding information bits to derive a cyclically encoded group of code bits from the information bits that were encoded, using a computer processor. A sequence of data states are generated that are the result of a series of exclusive OR operations of each of the code bits with each of the bits of a first generator word and bitwise ANDing each of the resultant bits with the results of the next previous such exclusive OR operations shifted in the direction of the least significant bit ("LSB") so as to generate a data state. The invention involves the following steps. First, an initial data state of zero is provided. Next, the LSB of the code bits is bitwise exclusive ORed with the current data state. Next, the result of the previous step is bitwise ANDed with the value n, where n is a selected binary value 2.sup.x -1, where x is any positive integer. Next, the current data state is changed to the next sequential data state by changing the data state to one of 2.sup.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: January 19, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Natarajan Seshan
  • Patent number: 5850403
    Abstract: Based on the sequence of the information bits to be transmitted, the coder forms a second sequence of bits c.sub.n, which includes a redundant subset. A differential coding of the form d.sub.n =c.sub.n .sym.d.sub.f(n) with f(n)<n produces a third sequence of bits d.sub.n. The signal sent represents the bits of the third sequence in a specified order. Having obtained likelihood data r.sub.n associated with the bits d.sub.n, the receiver calculates estimates of the bits c.sub.n of the redundant subset as a function of the sign of r.sub.n .multidot.r.sub.f(n). By exploiting the redundancy, the receiver can detect the bits c.sub.n of the subset having erroneous estimates, and rectify the sign of the less reliable of the two associated likelihood data items r.sub.n and r.sub.f(n). The other bits c.sub.n ' of the second sequence then benefit from additional protection if there is at least one bit c.sub.n of the redundant subset such that n'=f(n) or f(n')=n or f(n).
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: December 15, 1998
    Assignee: Matra Communication
    Inventor: Xavier Lasne
  • Patent number: 5841655
    Abstract: A method and system for item exposure control in computer based testing. A set of exposure control parameters representing the probability that an item selected from an item pool is administered to a test taker for each item in the pool is generated through computer based test simulation. The exposure control parameters can be initialized using values less than one that reflect the expected value after the test simulations are complete. The items in the item pool are ordered from most desirable to least desirable to administer based on predefined criteria. The set of exposure control parameters are used to generate operant probabilities associated with each of the items and represent the probability that the item is selected to be administered given that no more desirable item has been administered first. Items are randomly selected to be administered based on their corresponding operant probabilities.
    Type: Grant
    Filed: April 8, 1996
    Date of Patent: November 24, 1998
    Assignee: Educational Testing Service
    Inventors: Martha L. Stocking, Charles Lewis
  • Patent number: 5831860
    Abstract: It is possible to redirect a package in mid-transit, so as to deliver it to the addressee who will not be at the location to which the package was originally addressed when the package would otherwise be delivered. To do so, a package carrier, prior to delivering a package to an address specified by the sender, determines if the addressee desires the package to be rerouted to a different address. This determination is prompted by detection of the fact that the addressee is not in the vicinity of the address specified by the sender. The location of the addressee is determined from the location of a two-way pager associated with the addressee as detected by a paging antenna, e.g., tower, of a conventional two-way paging. A comparison is made between the location of the addressee and the address specified by the sender. If there is a disparity and the addressee subscribes to the package special delivery redirection service, the package is then processed according to the instructions of the addressee.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: November 3, 1998
    Assignee: AT&T Corp.
    Inventors: Mark Jeffrey Foladare, Shelley B. Goldman, David Phillip Silverman
  • Patent number: 5825648
    Abstract: A backup system for a time of day clock in an electronic device that enables a microprocessor to accurately maintain the time of day clock in the event of a power interruption. The backup system can be used with any AC powered electronic device that maintains a clock. The backup system allows a capacitor to supply backup power to the microprocessor and insures the accuracy of the clock by accounting for component tolerances in the system. The backup system calibrates the time constant of an RC circuit connected to the microprocessor while AC power is still available and stores that value for later use in determining the length of a power interruption. The calibration process allows the system to use lower cost components with higher tolerance values without compromising the accuracy of the time of day clock.
    Type: Grant
    Filed: March 26, 1996
    Date of Patent: October 20, 1998
    Assignee: Casio PhoneMate, Inc.
    Inventor: Mark J. Karnowski
  • Patent number: 5790569
    Abstract: There is provided a method of processing data for generating an error correction product code block devised so as to maintain the current level of redundancy after the error correcting ability is modified as a result of advancement of simiconductor and data recording/transmission technologies. Unlike any known technique of configuring a Reed-Solomon error correcting product code block of (M+P0).times.(N+PI) bytes for an information data of (M.times.N) bytes, an error correcting product code block data structure is obtained by configuring a (K.times.(M+1).times.(N+P))-byte Reed-Solomon error correcting product code block for (K.times.M.times.N)-byte data, making K variable to consequently make the entire size of the Reed-Solomon error correcting product code block variable. At the same time, the error correcting ability varies in proportion to the value of K without increasing redundancy.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: August 4, 1998
    Assignees: Kabushiki Kaisha Toshiba, Matsushida Electric Industrial Co., Ltd.
    Inventors: Tadashi Kojima, Koichi Hirayama, Yoshihisa Fukushima, Takashi Yumiba
  • Patent number: 5781567
    Abstract: Error-correcting apparatus and method for detecting and correcting a burst error affecting a plurality of reproduced signals representing adjacent data words groups the signals, calculates syndromes, determines the positions of errors in the reproduced signals and detects burst errors.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: July 14, 1998
    Assignee: Sony Corporation
    Inventors: Yoichiro Sako, Satoshi Otsuka, Tamotsu Yamagami
  • Patent number: 5781563
    Abstract: For a defective functional unit (FE1), it is possible to switch over via electronic input and output changeover switches (EUS1, AUS1) via a combination unit (KOM) to a substitute functional unit (EFE). The input signal (ES1) is supplied via a combiner (VK1) to the substitute functional unit (EFE) and is supplied via a splitter (VK2) to the output changeover switches (AUS1, . . . ), and is connected through only by the output changeover switch (AUS1) of the defective functional unit (FE1).
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: July 14, 1998
    Assignee: Siemens Aktiengesellschaft
    Inventors: Friedrich Schalamon, Kunihiko Iki
  • Patent number: 5777903
    Abstract: A smart card (50) transfers information between the smart card and an external system (24) while having the capability of being accessed by a user. The smart card includes a microprocessing unit (MPU) (18) for executing instructions stored in memory, a display (28), coupled to the MPU, for displaying information, a keypad (26), coupled to the MPU and to the display, for entering data by the user, an interface (54,56) for transferring signals between smart card and the external system when the smart card is coupled to the external system, and photovoltaic cells (52) for providing power to the smart card when the smart card is exposed to light. The smart card does not require the use of a bulky and inflexible battery and since the solar cells used are flexible, the flexibility of the smart card is maintained.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: July 7, 1998
    Assignee: Motorola, Inc.
    Inventors: Gerald V. Piosenka, Thomas M. Fox, Kenneth H. Schmidt
  • Patent number: 5761220
    Abstract: An asynchronous data path controller for reading, correcting, and transferring data on-the-fly from a digital recording device to a host system. Central to the data path controller is a RAM for storing the data as it is read from the recording device and a RAM controller for arbitrating access to the RAM. An error correcting system reads the data from the RAM, corrects the data, and then restores the corrected data back to the RAM before it is transferred to the host system. The error correcting system includes an error syndrome generator and a error location and error value generator. In a first embodiment, the data codewords, comprised of user data and redundancy symbols, are stored from the recording device into the RAM. The error syndrome generator reads the codewords from the RAM, generates error syndromes, and transfers the error syndromes to the error location and error value generator. In an alternative embodiment, the error syndrome generator receives the codewords directly from the recording device.
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: June 2, 1998
    Assignee: Cirrus Logic, Inc.
    Inventor: Christopher P. Zook
  • Patent number: 5761221
    Abstract: A method and apparatus for performing digital signal error detection and correction through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received. Errors are corrected and detected through assignment of data bits to different modules in a memory of a computer system having symbols which are b bits in length.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventors: Klaus Ruediger Baat, Chin-Long Chen, Mu-Yue Hsiao, Walter Heinrich Lipponer, William Wu Shen
  • Patent number: 5719883
    Abstract: Increased numbers of multipath transmission errors, that are detected by the performance of cyclic redundancy checking (CRC) over time and frequency on the words of a multitone transmission block that include mapped information bits, are correctable by forward error control as a result of the iterative performance of CRC over frequency on subblocks of the transmission block using retransmitted parity checking bits. A continuous record is maintained of the frequency channels that are detected as experiencing transmission errors in order to maximize the rate of data bit transmission on frequency channels that are likely to experience a reduced number of transmission errors.
    Type: Grant
    Filed: September 21, 1994
    Date of Patent: February 17, 1998
    Assignee: Lucent Technologies Inc.
    Inventor: Ender Ayanoglu