Abstract: A directory-search system for an LDAP server is provided to permit faster and more efficient persistent searches of LDAP directories of the server. Directory searches are performed by a proxy interoperably connected to one or more LDAP directories of the server and to one or more clients of the LDAP directories. The proxy searches a portion of the LDAP directories and receives registrations from one or more of the clients. The proxy can combine registrations from multiple clients into a single search of the LDAP directory. Registrations by the clients can be restricted to the portion of the LDAP directories searched by the proxy. The LDAP directories respond to the searches by the proxy by notifying the proxy concerning modifications to entries in the LDAP directories. In response to a determination that modified entries in the LDAP directories matches registration criteria received from one or more clients, the proxy notifies the appropriate clients of the modified entries.

Abstract: An Internet/Intranet World Wide Web (Web)-based centralized common interface repository system for event notifications and report outputs generated by different server applications and/or application platforms is provided as a message center. Such message center includes a common graphical user interface to a customer for viewing and receiving the report outputs and event notifications. The report outputs and event notifications are communicated in priority order using multithreading and multiprocessing mechanism wherein multiple messages may be serviced or received simultaneously. An Internet/Intranet Web-based information delivery system infrastructure capable of providing for the secure initiation, acquisition, and presentation of information from any customer computer platform having a Web browser is also provided.

Abstract: An occurrence capability which allows a first function to "go to sleep" while waiting for a second function to produce a result. In this manner, the first function does not consume any CPU time while waiting for the second function. Three icons are provided with associated control software which implement the occurrence function. A Wait on Occurrence function icon is associated with the first function that is waiting on the result from the second function. A Set Occurrence function icon is typically associated with the second function icon and triggers an occurrence when the second function produces the desired result. A Generate Occurrence function icon is used to pass identifier values linking multiple sources and destinations having Set Occurrence and Wait on Occurrence function icons, respectively.

Abstract: Apparatus for determining the length of an instruction being processed by a computer system when instructions vary in length and appear sequentially in an instruction stream without differentiation between instructions including apparatus for providing an end bit for each predesignated length of an instruction to indicate that the instruction ends at that point in its length, apparatus for setting the end bit at the particular predesignated length of the instruction which is the actual end of the instruction, a first channel for processing a first instruction in sequence, a second channel for processing an instruction next following the first instruction, and apparatus for looking at the end bits of an instruction being processed by the first channel to determine the end point of that instruction and the beginning of the next instruction from the stream of instructions.

Abstract: A data processing system is described utilising multiple instruction sets. The program instruction words are supplied to a processor core 2 via an instruction pipeline 6. As program instruction words of a second instruction set pass along the instruction pipeline, they are mapped to program instruction words of the first instruction set. The second instruction set has program instruction words of a smaller bit size than those of the first instruction set and is a subset of the first instruction set. Smaller bit size improves code density, whilst the nature of the second instruction set as a subset of the first instruction set enables a one-to-one mapping to be efficiently performed and so avoid the need for a dedicated instruction decoder for the second instruction set.

Abstract: A bypass mechanism within a register alias table unit (RAT) for handling source-destination data dependencies between operands of a given set of operations issued simultaneously within a superscalar microprocessor. Operations of the given set are presented in program order and data dependencies occur when a source register of particular operation is also utilizes as a destination register of a preceding operation within the given set of operations. At this occurrence, the initial read of the RAT unit will not have supplied the most current rename of the source register. The present invention includes a comparison mechanism to detect this condition. Also included is a bypass mechanism for bypassing the physical source register output by the initial read of the RAT unit with a recently allocated physical destination register assigned to the preceding operation having the matched physical destination register.

Abstract: A car built-in type one-chip microcomputer including a ROM, a RAM, and an input/output port, wherein a control program which is executed on the car built-in type one-chip microcomputer is stored in a high level language, so that formation, change and verification of a control program can be easily carried out by an ordinary programmer who has never been trained to treat an assembly language. Even if the kind of the microcomputer is changed, it is not necessary to change the control program. The program can be modified as a result of experiment. A program developed by a program developing apparatus can be used, as it is compatible with the microcomputer.

Abstract: A hierarchical structure processor including a memory for storing processing instruction code data described sequentially; a main CPU for fetching and decoding the processing instruction code data and generating an executing sequence, the main CPU having buses for transferring instructions, data control signals; and a plurality of sub CPUs connected to the main CPU through the buses for executing basic instructions received from the main CPU. The main CPU includes a bus controller for sending a macro instruction indicative of the basic processing to one of the sub CPUs and for receiving an execution result of the processing designated by the macro instruction from the sub CPU. The bus controller waits for a READY signal from the associated sub CPU having the execution result.

Abstract: Disclosed is an arrangement for "seamlessly" integrating telephone services relative to primitive analog telephone equipment into general purpose computer systems. The integration is effected through present "secondary" adaptation of data link control adapter devices which are adapted primarily for coupling such computer systems to high speed data communication links for transmission and reception of digital data. This permits general resources of the computer system (keyboard, memory, disk drives, etc.) to be used for specific applications associated with telephone services. Presently described link control devices have a telephone attachment port which couples through analog-to-digital conversion circuits to a primitive analog telephone (no dial or keys). Such devices operate normally in time division multiplex to process communication data between a computer (host) system and data link ports.

Abstract: An information processing system has a first processing apparatus and a detachably connected second processing apparatus. The first processing apparatus has an input unit for entering information and commands, a first processor for executing a process based on the information and command entered from the input unit, and an output unit for releasing the results of such execution, while the second processing apparatus has a second processor for executing a process based on the information and commands entered from the input unit and transferring the results of that execution to the output unit. The second processing apparatus can execute a process which cannot be executed by the first processing apparatus, utilizing the input/output equipment of the first processing apparatus.

Abstract: A self-timed data streaming receiver for a routing chip. Incoming flits are received by a distributor that distributes the flits between two self-timing FIFOs. A collector coupled to both FIFOs at their opposite ends takes the two streams of flits and recreates the original stream of flits prior to coupling the flits to routing control circuitry. A self-timed data streaming transmitter is also described.

Abstract: This invention is a data processor including a data transfer controller. The data transfer controller includes internal and external memory interfaces coupled to internal and external memory, respectively. A pipeline controller controls the internal memory interface and the external memory interface. A source address generator generates addresses for reading data. A destination address generator generates addresses for writing data. Buffer circuitry interposed between the source address generator and the destination address generator permits data to be aligned to differing source and destination data word sizes and differing data word boundaries. An external sequencer provides control signals for the external memory via the external memory interface. In the preferred embodiment, the buffer circuitry includes a first-in-first-out (FIFO) buffer having a plurality of registers. This permits continued operations in many cases when either the source or destination memory operations temporarily stall.

Abstract: A bypass mechanism within a register alias table unit (RAT) for handling source-destination dependencies between operands of a given set of operations issued simultaneously within a superscalar microproessor. Operations of the given set are presented in program order and data dependencies occur when a source register of particular operation is also utilizes as a destination register of a preceding operation within the given set of operations. At this occurence, the initial read of the RAT unit will not have supplied the most current rename of the source register. The present invention includes a comparison mechanism to detect this condition. Also included is a bypass mechanism for bypassing the physical source register output by the initial read of the RAT unit with a recently allocated physical destination register assigned to the preceding operation having the matched physical destination register.

Abstract: A method and system are disclosed for efficiently translating data from one known data sequencing arrangement to an alternative sequencing arrangement. The method consists of the steps of generating a source sequence signal which identifies the ordering of units within the source sequence, generating a destination sequence signal which identifies the ordering of units within the destination sequence, and combining the source signal and destination signal to produce a permutation signal which defines the relationship between the source sequence and the destination sequence. Once the permutation signal has been defined, this permutation signal is applied to the source sequence to allow the reordering of the source sequence into the desired destination sequence. A reordering circuit is used to rearrange the source sequence units into the desired destination sequence units utilizing the permutation signal generated in the present invention.

Abstract: While a busy state is indicated in a status register by a first busy signal kept active while a command is stored in a parameter register group as a stored command, a free state is indicated while a second busy signal is kept inactive until later kept active while a parameter group is stored in the parameter register group as a stored parameter group. After lapse of the free state during which a command executing unit is operable without reference to the stored parameter group, the unit is operable by using a working register group alone. Furthermore, a like parameter group can be stored in the parameter register group, which is connected to a bus through a multiplexer while the second busy signal is inactive. During a short interval during which the first busy signal is inactive and before the second busy signal is activated, another command can be stored through the multiplexer. A logic circuit can be used instead of the status register.

Abstract: Systems and methods for providing graceful insertion of a station or tree into a ring type network. According to one aspect of the invention, graceful insertion is achieved after coupling a tree to a tree link of a master port by switching the tree into a local ring, holding the local ring, and awaiting a token on the network ring. After a token is received on the network ring, the tree is switched from the local ring to the network ring. Monitoring ring status in hardware provides the responsiveness necessary which software graceful insertion typically cannot provide.

Abstract: A data processor and a data transfer method for efficiently transferring data between a plurality of information processing devices as in a client server system. In case non-coded data such as image data are transmitted, it is necessary to make the transmission management requirements such as protocol, data structure, coding scheme, and coding default condition coincide between the transmitting side and the receiving side. In order to satisfy this requirement, a data processor lying between a plurality of information processing devices and having a data transfer intermediary function records beforehand transmission management information including identification information concerning a plurality of clients, discriminates a client by using the identification information, and recognizes transmission management information concerning the discriminated client.

Abstract: A parallel processing system consists of a plurality of processor elements and a network for connecting the processor elements to each other. The processor includes a processor, a memory and a data transfer apparatus, all connected to a common bus. The data transfer apparatus includes of three buffers, while a data relay includes two buffers. In data transfer from a processor element to another processor element, a data is relayed in a third processor element only with use of a buffer, or a write/read operation is not performed in the third processor element. Then, the overhead is decreased and the transfer capability is improved. Further, the data transfer apparatus does not access the common bus, so that the width of the bus can be increased, and the processing performance of the processor can be improved.

Abstract: A distributed computing system having a distributed protocol stack. In a system including one or more general purpose computers or other application processors for running applications, the distributed protocol stack off-loads communication or other I/O processing from the application processor to dedicated I/O processors using a STREAMS environment thereby enhancing the performance/capacity of the system. The distributed protocol stack is formed of a STREAMS stack top and a stack bottom so that together the stack top and stack bottom comprise a full stack functionally equivalent to a non-distributed stack running on an application processor. Both the application processors and the I/O processors together appear to execute the full protocol stack, but the application processor only executes the stack top while the I/O processor only executes the stack bottom.

Abstract: A plurality of system buses are provided in association with multiple processors and a memory, respectively. Registers are provided between the system buses so that a packet signal can be sent, in a pipelined form, to bus interfaces connected to the respective system buses. Each bus interface is assigned its own ID value. Counting the number of ID values cyclically at the rise of a clock signal, each register asserts a bus-ID match signal when finding coincidence of the bus-ID value. In response to the asserting of the bus-ID match signal, the associated bus interface provides the packet signal to the system bus. When the bus-ID signal is negated, the associated bus interface takes in the packet signal from the system bus.