Abstract: A circut arrangement for serial data transfer has a transmitting device with several bit-parallel input information units, a serial data transfer line and a receiving device via which the transferred data are correspondingly converted into bit-parallel output information units to drive control elements or logic circuits. The data to be transferred forms on the data transfer line a data word composed of a start pulse, several information units corresponding to the number of bit-parallel input information units forming a data block, and a defined data pause. By cascading several transmitting and receiving devices of the same kind, the number of bit-parallel, input and output information units can be altered, whereby the data word on the data transfer line is also altered by sequential joining of a corresponding number of data blocks, each having the same number of information units.

Abstract: A mapping-type data signal optimizer performs a multi-pass scan to optimize multiple-plane symbol buffers. A total of seven scanning passes of the difference map planes is made: A triple-plane scan in search of white characters; three dual-plan scans in search of turquoise, yellow, and pink characters, respectively; and three single-pass scans in search of red, blue, and green characters, respectively. This minimizes the length of the output signal required to effect the changes to the multiple planes. The optimizer performs an MDT-reset voting routine to determine whether selective setting of modified data tags (MDTs) can be done more effectively by (a) clearing all MDTs and individually setting desired MDTs, or (b) clearing desired MDTs. The approach resulting in the shorter signal is utilized.

Abstract: There are provided a backup version page table in a storage for providing a correspondence between the pages of a database and the slots in a database storage medium in which the contents of pages to be recovered, if necessary, are stored; a current version page table for providing a correspondence between pages updated by a transaction and slots in the database storage medium wherein the updated contents of the pages are stored; and a journal file for recording various system journals; wherein the updated page contents are stored in the database stored medium at the slots not-used at that time and found with reference to the backup version page table and the current version page table.

Abstract: An image processing system has sixteen processing assemblies provided by transputers which each have a memory and a processor. An infra-red television camera supplies signals representing different areas of the field of view to respective different ones of the processing assemblies. The assemblies also receive external signals from other sources and are interconnected with one another by a line which enables synchronization between the assemblies. Each processor processes only that information in its memory and provides output signals representative of the respective area of the field of view.

Abstract: A system for preparing shipping documents includes a processor, a keyboard, a display, a memory and a printer. Associated with the printer are a single sheet feeder, a batch feeder and an endless form feeder. The system is capable of preparing a wide variety of waybills and other shipping forms. The system is also able to prepare automatically all shipping documents required for a mass shipment to a user-defined group of recipients. A user activated "help" function provides information specific to the type of data that the user is attempting to enter at the time the help function is activated. There is also a "rare shopping" function that allows the user to define for each shipping mode a group of other shipping modes for rate comparison purposes.

Abstract: The wafer scale integrated circuit comprises an array of undiced chips or modules, each of which includes a data storing or processing circuit, e.g. a dynamic RAM, and configuration logic. Channels for data and control signals exist between each module and its (N, S, E and W) neighbors and a target module in the array may be addressed by setting up a path through the array from an entry module to the target module. The addressing is effected by sending a stream of link commands, each of which tells a module to link on to its (N, S, E or W) neighbor. Each module responds to the first command of the stream and then sends on the stream stripped of this first command. In an alternative embodiment the link commands are transmitted from module to module in parallel, each module responds to the command at the least significant end and strips it off by a shift of the commands in the least significant direction before the commands pass to the next module.

Abstract: A digital data processing system includes a plurality of processing subsystems, each including an adapter for enabling transfers between the resident subsystem and other subsystems. The adapter includes a master section which enables transfers of data initiated by the subsystem between the input/output bus and the higher level communications mechanism, a slave section which enables transfers of data between the higher level communications mechanism and the input/output bus initiated by another subsystem and an interprocessor communications mechanism for enabling the subsystem and other subsystems to communicate to thereby enable the other subsystems to perform control operations in connection with the subsystem.

Abstract: A high availability set associative cache memory for use as a buffer between a main memory and a central processing unit includes multiple sets of cache cells contained in two or more cache memory elements. Each of the cache cells includes a data field, a tag field and a status field. The status field includes a force bit which indicates a defective cache cell when it is set. Output from a cache cell is suppressed when its force bit is set. The defective cache cell is effectively mapped out so that data is not stored in it. As long as one cell in a set remains operational, the system can continue operation. The status field also includes an update bit which indicates the update status of the respective cache cell. Replacement selection logic examines the bit pattern in all the cache cells in a set and selects a cache cell to be replaced using a first-in first-out algorithm.

Abstract: This invention is an image processing system which includes an input controller having a CPU adapted to dot and compress density or tone data for an image read out by an input unit and for temporarily staying said compressed image data at a buffer; a work station providing a second CPU adapted to picture-edit not only a code information edited by an editing input unit but also the image data by the use of an input operating means and a display means; a file server including a third CPU connected to the input controller and the work station by bus lines and for storing the image data, code information and edited data picture-edited by the work station in the file server; and an image setter having a fourth CPU for reading out the edited data stored in the file server and subjecting the edited data to a required data processing, thereby outputting an image over an image output unit characterized in that the input controller, the file server, the work station and the image setter are individually and independent

Abstract: For filling the area bounded by a two-dimensional geographic shape, a so-called graphic, with light from a scanning beam, a reduced size graphic is created within the original graphic. The reduced graphic is divided into convex loops by being divided up along a set of lines which extend parallel to a predetermined direction (Y). The respective longitudinal directions of the convex loops are detected, and then, alternate vectors are generated along the respective longitudinal directions of the convex loops. The scanning beam is moved along the vectors on a photosensitive film, thus filling the inner region of the graphic with the traces of the light beam.

Abstract: A pocket size data storage apparatus with a tablet device for inputting image data, of the present invention, has a display section of a dot matrix type, and a tablet device made of transparent members and mounted on this display section as one unit. Image data is input from the tablet device and displayed on the display section. Character data input by operating the character keys can be displayed together with the image data. Image data and character data are related to each other as a pair of data and are stored.

Abstract: In a publishing system for editing documents having a processing unit, inputting device and a display screen, the document parts (components) are provided with properties which describe their appearance, and each individual component belongs to a component type. The component types and the individual components of that type have corresponding properties, the values of which can be set by the system operator. The value of a property of an individual component is usually identical to the value of the corresponding property of that type but may also be set to differ locally therefrom. This is indicated on the screen. On a change of the value of a property of a component type the value of each individual component of that type is changed similarly unless that value had been set to be locally different.

Abstract: A method of displaying acquired data where a full screen base line display is scaled to represent the total duration of a device under test. Acquired data points are positioned on the base line display at locations proportional to their time of occurrence in the test. Icons, symbolic of the type of event associated with the acquired data points, are shown on the base line display. A movable bifurcating cursor points to the events and associated alphanumeric displays give distance and type of event information.

Abstract: A display apparatus and a modelling method for computer graphics includes a first memory for storing a first three-dimensional model, a detailed model, of a body represented by at least one of desired first number of dimensions, a desired first number of parameters and desired first parametric quantities, an arithmetic unit for arithmetically determining a second three-dimensional model, a simplified model, by varying at least one of the first number of dimensions, the first number of parameters and the first parametric quantities to at least one of a second number of dimensions, a second number of parameters and second parametric quantities in accordance with an algorithm for thereby creating automatically a simplified model for a body of less importance. A second memory stores the simplified model. A selector selects the first three-dimensional model or the second three-dimensional model by reference to a preset index for evaluation.

Abstract: A printer for receiving print instructions from one of a plurality of host units includes an input data storage unit for storing the data including control codes and character codes input by the selected host unit. At least two print control units having internal character code/control code groups process the data in the input data storage unit in accordance with the internal control codes. A character code/control code judging unit decodes the plurality of character codes/control code groups stored in the input data storage unit and determines which print control unit is to process the data by comparing the input control code groups with the internal control code groups of each print control unit.

Abstract: An electronic translator comprises a memory circuit for storing words which is removable from the translator, an attachment connectable to the translator, and a coupling device permitting either the memory circuit or the attachment to be connected to the translator. The coupling device is provided within the translator. The attachment may be a printer or an audible sound generator.

Abstract: Herein disclosed is a serial data transfer system which has first and second serial data processors connected via a single data line and a single clock line for transferring serial data therebetween. Each of the first and second serial data processors includes: reception confirmation signal output means for outputting a reception confirmation signal to the data line; and reception confirmation signal detection means for detecting the reception confirmation signal on the data line. The confirmation of the data transfer is executed in synchronism with serial clock pulses outputted to the clock line. Alternatively, the first or second serial data processor includes: an output circuit for outputting a reception confirmation signal to the data line; a circuit for generating a first signal indicating the end of reception of the serial data; a circuit for generating a second signal indicating the end of processing of the data received; and a circuit for controlling the output of said reception confirmation signal.

Abstract: A data processing system includes a workspace network data structure, such as a hypertext data structure, in which data units corresponding to displayable workspace sets such as cards are linked by linking data units. The data structure also includes a link creation data unit associated with one of the cards. When that card is displayed, a selectable link creation unit, called an AutoLink button, corresponding to the link creation data unit is also displayed. When the user selects the AutoLink button, the link creation data unit is accessed to obtain data for creating a link to another card. The data structure also includes a card creation data unit that is also accessed to create the destination card for the link. An AutoLink button can be repeatedly selected to create several new cards and links between each new card and the card with the AutoLink button.

Abstract: In a time chart plotter which uses a liquid ink supply (such as an ink jet plotter) the computer program in the plotter microcontroller is modified so that for any one increment of chart movement, each point in the other dimension (i.e., the signal axis) is plotted only once. This conserves ink and also prevents heavy buildup of ink on the chart.

Abstract: A multi-colored dot matrix display device and its controller which has a microprocessor and address buffers, data buffers and video memory planes. Each video memory plane has an associated address buffer and an associated data buffer. A graph control data circuit controls each video plane of memory and a colored pallet to control the display, on the dot matrix display device. The pallet control circuit is used to determine the actual color which is displayed from each video memory plane which controls the final color which is displayed on the dot display device.