Abstract: An apparatus for maintaining a history of instructions which have been most recently executed by a digital computer. A push-down stack is utilized for storing the contents of the program address counter, or the operand portion of the instruction register, of the computer upon the execution of every instruction and then pushing down the push-down stack whenever the last instruction executed by the digital computer was a branch type instruction. Provision may also be made for addressing the push-down stack so that the contents thereof may be reviewed in the order opposite from which it was loaded. This apparatus allows a user or diagnostic program to have access to the address of the most recently executed branch type instructions. In this way, a history of the most recently executed instructions can be maintained to aid hardware and software diagnostics.

Abstract: In order to provide for coherence of exchanges between a block of data of a ower speed level and several blocks of data of a contiguous level of higher speed, a control table of the block of the lower speed level registers page by page at least those blocks of the higher speed level which have received extracts from those pages; a control table of each of the blocks of the higher speed level registers by itself, page by page, the number of those extracts and also registers the validity of the data contained in its block, and preferably also the modifications of those data, and in certain cases the exclusion of access of other blocks of the higher speed level to those data; and an organization of the control of these data makes it possible to provide for the required coherence, starting with the information identified above.Applications: Information science systems with a hierarchy of memories.

Abstract: A programmable sequence control device for programming a control sequence by simulating the steps of a flow chart comprises a plurality of stages each of which is visually representative of a step in the flow chart and is selectively wired to other stages for simulating the flow chart. The stages comprise contact points representing output terminals, address terminal and jumping control terminal, respectively. A logic control circuit between each two stages at the respective contact points comprises first logic means producing a first output signal based on the combination of signals at the output terminal and jumping control terminal of a first stage and second logic means responsive to an address signal applied to the address terminal of another stage for producing a further output signal applied at the output terminal of the latter stage. Upon application of a starting command at a selected stage, the stages sequence through the steps simulating the operations of the intended flow chart.

Abstract: An address management system includes a central processing unit (CPU) and an address management unit arranged between a direct memory device (DMA) and a main memory unit to control memory access from the CPU and DMA. Segment registers for address expansion are provided in the CPU and DMA, respectively. The address management unit includes a conversion table for converting logical address data and segment data and segment data from the CPU and DMA into a corresponding physical address data, and the conversion table includes a bit position for detecting an address error and a control bit for selecting a memory access to a local memory or a shared memory.

Abstract: An Input-Output Interface Data-Transfer Control Unit, designated as a Line Control Processor, which provides the execution of instructions in accomplish data transfers between a main data processing system and a plurality of different types of peripheral devices. Further, said Line Control Processor provides for the buffering of at least two complete blocks of message data, thus to prevent access errors, since complete record length message transfers can occur in any given data-transfer cycle. The Line Control Processor operates with a standard communications and control discipline which makes the eccentricites of various types of peripheral units transparent to the main system. The Line Control Processor executes data-transfer instructions within the overall system thus relieving the central processor of an involvement in these tasks.

Abstract: A data processing system is disclosed which includes a control system with a buffer store connected to a central processing unit to receive data items before they are transferred to a secondary journal store. A monitoring system keeps a check on the rate at which data items are placed in the buffer store by setting a sample value, which is a count of the accumulated size of items in the buffer store, and a sample time which is a period, such as one second, considered a reasonable waiting time for a transaction, either of which when reached can cause the contents of the buffer to be transferred to the secondary journal store. If the sample time is reached before the sample value, then the value is increased.

Abstract: A memory expansion apparatus is disclosed which provides for expansion of memory capacity by use of logic associated with memory modules. The logic provides for selection of one of a plurality of pages, each having substantially the same address therefor. The device provides for the selection by utilization of a special instruction, and includes decoding means for specialized bits in the instruction. Means are provided wherein repeated access to the same page in a block occurs free of a requirement of repeated address decoding amongst the plurality of pages in the block.

Abstract: A data processing system includes a plurality of system units all connected in common to a system bus. The system units include a central processor (CPU), a memory system and a high speed buffer or cache system. The cache system is word oriented and comprises a directory, a data buffer and associated control logic. The CPU requests data words by sending a main memory address of the requested data word to the cache system. If the cache does not have the information, apparatus in the cache requests the information from main memory, and in addition, the apparatus requests additional information from consecutively higher addresses. If main memory is busy, the cache has apparatus to request fewer words.

Abstract: A digital processor which may be used in a calculator is provided by an MOS/LSI semiconductive chip which contains a bit-parallel arithmetic unit for operating on data stored in a random access memory. Selector units determine which of several sources produce the inputs to the arithmetic unit. The random access memory has X and Y, or page and word addressing. Part of the random access memory provides direct access for readout. Numerical data at the Y address in the direct access memory is always available at the selector units for input to the arithmetic unit, at the same time that data at the same Y address but another X address is read out to be also an input to the arithmetic unit. The direct access part of the memory is addressed for write in by the same addressing means as the remainder of the memory. This arrangement reduces the number of machine cycles needed for arithmetic operations, and so provides faster calculations.

Abstract: A circuit for sequencing microinstruction sequences in data processing equipment in which during the course of a primary sequence subroutine jumps are performed and subsequences are carried out and at the end of each, a return jump into the primary sequence takes place due to the control provided by a temporarily stored return jump address at a point in the sequence at which a two-part branching instruction is to be evaluated. The first part of the branching instruction characterizes a branching function which is to be carried out dependent on a decision which is specified in the second part thereof. The circuit includes a microinstruction storage from which microinstruction sequences are taken over depending upon the output signals from a central fixed-cycle control circuit fed into a microinstruction register and a recoder which is arranged thereafter.

Abstract: A sensor based system, such as a building management system, includes a central processor and an associated subsystem comprising at least a central panel interconnected with a plurality of remote panels, each of the remote panels being capable of further interconnection with a variety of devices for monitoring and control purposes. The subsystem is essentially a digital input/digital output (DI/DO) multiplexer comprising a central panel and from one to fifty remote panels, as an example. A simplified interconnection technique is provided in the subsystem for achieving efficient addressing of the remote panels and their associated sensor devices together with transmission of control and monitoring information. Control signals and status or other indications are handled by manual or computer intervention. Input/Output (I/O) cards are included that provide for all functions required for interfacing the multiplexer subsystem to the individual sensor devices.

Abstract: The disclosure describes a floating-priority storage access control arrangement for plural processors to a shared main storage in a multi-processing (MP) system. The shared main storage logically couples the main storage units provided with each of the processors into a single expanse of real addresses available to each processor. Exclusive access to the shared storage is given to any processor for as long as that processor can provide a burst of one or more successive storage requests. The burst ends when that processor misses a storage cycle by not providing a locally granted request.The shared storage access is controlled in each processor by means of an MP priority pointer circuit which receives storage requests granted by a local priority circuit in the processor. The MP priority pointer circuits are interconnected between the processors.

Abstract: An electronic calculator or microprocessor system is provided with a semiconductor chip having a prechargeable and conditionally dischargeable instruction word memory, a program counter for addressing the instruction word memory, and a power up clear circuit. The power up clear circuit includes a latch circuit having two states, the first state being preferentially entered on when electrical power is first provided to the latch circuit and a second state which is entered at some time thereafter, and a gating circuit for interrupting the addressing of the instruction word memory by the program counter when said latch circuit is in the first state.

Abstract: A plurality of logic circuits having log in-out functions are connected in sequence. A clock distribution circuit is connected to each sequential logic circuit via a corresponding one of a plurality of bidirectional lines. A mode designation signal is supplied in common to each sequential logic circuit and the clock distribution circuit. A sequential logic circuit selection signal, which selects one of the sequential logic circuits, is supplied to the clock distribution circuit. A clock signal is supplied from the clock distribution circuit to each sequential logic circuit via the bidirectional lines in the clock mode. Log in data is supplied from the clock distribution circuit to the sequential logic circuit via a specific bidirectional line in accordance with the sequential logic circuit selection signal in the log in mode.

Abstract: A distributed data processing system having a magnetic disk and a master disk control and communication control unit; a slave work station unit having a keyboard for the input of data and a cathode ray tube display screen for the display of input data; and a slave output printer. The work station display is a CRT screen which can display 24 lines each of 80 characters, or a total of 1920 characters. The keyboard is similar to that of a standard electric typewriter with the addition of special instruction keys and keys for moving a cursor symbol on the screen. Optionally, other slave peripheral devices, such as a telecommunications link, a line printer, or a paper tape punch, may be provided. All slave units of the system are connected to the master unit by coaxial cables.Access to the disk for data reads and writes is under control of the master unit.

Abstract: This invention is directed to language translating apparatus and methods therefor which act, under program control, to enable automatic writing systems of the type disclosed herein, to be simply and easily adapted to operate with keyboard input peripherals which are standard outside the United States. The language translator apparatus herein permits the automatic writing system to be modified to accept the standard keyboard and print wheel arrangement employed in a plurality of countries merely by its inclusion as a peripheral and adapting the keys on the keyboard for a given country. When data is entered into the system at the keyboard, the language translator peripheral, which includes a plurality of translator ROM's, is active to translate the resulting input codes into recordable system codes to which the automatic writing system as a whole may respond.

Abstract: The present invention relates to a memory addressing mechanism which has been formulated to accommodate three address structures: real, based and virtual. To accomplish this result the address generation function in the memory addressing mechanism has been separated into two distinct parts, address computation and address translation. By merely changing the hardware components in the address translation part of the memory addressing mechanism and leaving the hardware in the address computation part constant, an optional memory addressing mechanism which supports either a real address structure, a based address structure or a virtual address structure can be implemented.Further, the present invention with the virtual address translation apparatus in cooperation with the fixed address computation apparatus provides a virtual addressing mechanism which will compute and retrieve a memory word utilizing a four-segment memory address with only two memory references.

Abstract: Audio data is converted into a digital format at a selectable conversion rate and applied through a microprocessor into memory storage. Stored data is selectively recalled and reconverted into an analog format for reconstruction into human speech at a processing rate independent of the input storage rate. The write pointer address and the read pointer address during the storage and retrieval of data are maintained within a selected address differential in accordance with the input data rate and the processing rate. To repeat the retrieval of particular stored data from selected address locations, the data input storage is interrupted thereby holding in memory a selected portion of previously stored data. The amount of data retrieved during the repeat process is varied by controlling the write pointer and the differential address between the write pointer and the read pointer.

Abstract: A system for distinguishing a digital signal in a received serial bit stream signal, and for displaying data represented by the distinguished digital signal is disclosed. The system is contained in a single console. The bits represent data in an original digital signal having a predetermined bit rate, a predetermined number of bits per word, a predetermined number of words per frame, and a predetermined number of frames per subframe, with there being a predetermined synchronizing code word in each frame for defining the frame. The system includes a processing network for processing the received signal to reconstruct the bits, to recognize the code word from the recognized bits, and to define the frames in response to recognition of the code word to thereby distinguish a digital signal having the predetermined number of bits per word, the predetermined number of words per frame, and the predetermined number of frames per subframe.

Abstract: A dot matrix converter comprising means for providing an original character pattern comprising a dot matrix; means for dividing the original matrix into row groups and column groups, the number of groups being respectively one greater than the row difference and the column difference between the original matrix size and a desired matrix size to which the original matrix is to be converted; row (or column) size converting means which compare the individual opposed bits in the rows (or columns) on the opposite sides of dividing lines between adjacent row (or column) groups and inserts a logical "1" bit between the compared bits when both bits are logical "1" or inserts a logical "0" bit in all other cases, thereby effecting the addition of one row (or column) between the divided adjacent row (or column) groups; and column (or row) size converting means which compare the individual opposed bits in the columns (or rows) on the opposite sides of the dividing lines between adjacent column (or row) groups, and inser