Abstract: A nanotube transistor, such as a carbon nanotube transistor, may be formed with a top gate electrode and a spaced source and drain. Conduction along the transistor from source to drain is controlled by the gate electrode. Underlying the gate electrode are at least two nanotubes. In some embodiments, the substrate may act as a back gate.

Abstract: A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.

Abstract: A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.

Abstract: Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance between the gate and the drain region. In another embodiment device destruction at high voltages is prevented by ballasting the FinFET. Specifically, resistance is optimized in the fin between the gate and both the source and drain regions (e.g., by increasing fin length, by blocking source/drain implant from the fin, and by blocking silicide formation on the top surface of the fin) so that the FinFET is operable at a predetermined maximum voltage.

Abstract: A solid-state imaging device includes: a plurality of N-type photodiode regions formed inside a P-type well; a gate electrode having one edge being positioned adjacent to each of the photodiode regions; a N-type drain region positioned adjacent to the other edge of the gate electrode; an element-isolating portion having a STI structure, and a gate oxide film having a thickness of not more than 10 nm. One edge of the gate electrode overlaps the photodiode region.

Abstract: An electronic module has a heat sink with an upper surface and a lower surface, a plurality of leads arranged adjacent the heat sink and at least one circuit element with two vertical semiconductor power switches. The two vertical semiconductor power switches of each circuit element are arranged in a stack and are configured to provide a half-bridge circuit having a node defining an output. The first vertical semiconductor power switch of each of the circuit elements is mounted on the upper surface of the heat sink by an electrically conductive layer such that the lower surface of the heat sink provides the ground contact area of the electronic module.

Abstract: There is provided a high-reliability nano-dots memory by forming the nano dots uniformly. Also, there is provided the high-speed and high-reliability nano-dots memory by employing a silicon-oxide-film alternative material as a tunnel insulating film. The nano-dots memory includes the tunnel insulating film and silicide nano-dots of CoSi2 or NiSi2. Here, the tunnel insulating film is formed by epitaxially growing a high-permittivity insulating film of HfO2, ZrO2 or CeO2 on a silicon or germanium substrate, or preferably, on a silicon or germanium (111) substrate. Also, the silicide nano-dots are formed on the tunnel insulating film.