Abstract: A semiconductor light emitting device includes: a light emitting structure including a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer respectively providing a first surface and a second surface, opposite to each other, of the light emitting structure, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, a region of the first conductivity-type semiconductor layer being open toward the second surface, and the first surface having a concavo-convex portion disposed thereon; a first electrode and a second electrode disposed on the region of the first conductivity-type semiconductor layer and a region of the second conductivity-type semiconductor layer, respectively; a transparent support substrate disposed on the first surface of the light emitting structure; and a transparent adhesive layer disposed between the first surface of the light emitting structure and the transparent sup

Abstract: A semiconductor device includes a semiconductor substrate provided with a through-hole, a device layer including a lower layer wiring, an insulating layer that covers the device layer, a first through-electrode that passes through the insulating layer, a first insulating film provided with an opening having a diameter that is substantially the same as or greater than an opening diameter of the through-hole of the semiconductor substrate, a second insulating film positioned on an upper side of the first insulating film and on an inner side surface of the through-hole of the semiconductor substrate, and a second through-electrode electrically connected to the lower layer wiring in the device layer from an upper side of the second insulating film through the inside of the through-hole of the semiconductor substrate.

Abstract: A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator. The first conductor includes a first region and a second region. The second conductor includes a third region and a fourth region. The second region faces the third region with the first conductor and the first insulator interposed therebetween. The second region is thinner than the first region. The third region is thinner than the fourth region.

Abstract: A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer.

Abstract: An organic light emitting display device includes a substrate, a gate insulation layer, a planarization layer, a boundary pattern, and a sub-pixel structure. The substrate includes a sub-pixel region and a transparent region. The gate insulation layer is disposed on the substrate. The planarization layer is disposed in the sub-pixel region on the gate insulation layer, and exposes the transparent region. The boundary pattern covers a boundary of the sub-pixel region and the transparent region. The sub-pixel structure is disposed on the planarization layer.

Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.

Abstract: Disclosed is a thin film transistor substrate capable of preventing a circuit from being damaged by static electricity, and a display device including the same, wherein the thin film transistor substrate includes a substrate having a display area for displaying an image, and a non-display area. The circuit is disposed in the non-display area. The circuit includes a first electrode, an insulating film on the first electrode, and a second electrode on the insulating film. An edge of the first electrode facing the display area extends beyond an edge of the second electrode facing the display area.

Abstract: A semiconductor storage device of the present embodiments includes a substrate, a first semiconductor chip and a sealer. The substrate has wirings. The first semiconductor chip is connected to the wirings on the substrate. The sealer has a first surface, which does not face a top surface of the first semiconductor chip and is provided with a mark, and seals the first semiconductor chip.

Abstract: An optoelectronic semiconductor chip is disclosed. In an embodiment the optoelectronic semiconductor chip includes a semiconductor body of semiconductor material, a p-contact layer and an n-contact layer. The semiconductor body includes an active layer intended for generating radiation. The semiconductor body includes a p-side and an n-side, between which the active layer is arranged. The p-contact layer is intended for electrical contacting the p-side. The n-contact layer is intended for electrical contacting the n-side 1b. The n-contact layer contains a TCO layer and a mirror layer, the TCO-layer being arranged between the n-side of the semiconductor body and the mirror layer.

Abstract: A semiconductor device includes a first semiconductor chip having a first surface, a second surface on a side of the first semiconductor chip opposite to that of the first surface, a first electrode on the first surface, a second electrode on the second surface, and a first contact electrically connecting the first electrode and the second electrode, and a second semiconductor chip having a third surface facing the first surface, a fourth surface on a side of the second semiconductor chip opposite to that of the third surface and a third electrode on the fourth surface. The semiconductor device further includes a metal wire electrically connecting the first and third electrodes, a first insulating layer on the second surface, a first conductive layer that is on the first insulating layer and electrically connected to the second electrode, and a first external terminal electrically connected to the first conductive layer.

Abstract: Apparatuses for coupling a semiconductor device to a cooling system, methods of coupling a semiconductor device to a cooling system, and systems incorporating the apparatuses are disclosed. An apparatus includes a first frame member coupled to the cooling system, a second frame member coupled via one or more fasteners to the first frame member, and a spring assembly disposed between the first frame member and the second frame member. The semiconductor device is disposed between the spring assembly and the second frame member.

Abstract: Systems and methods are disclosed for fabricating a semiconductor die that includes one or more bipolar transistors disposed on or above a high-resistivity region of a substrate. The substrate may include, for example, bulk silicon, at least a portion of which has high-resistivity characteristics. For example, the bulk substrate may have a resistivity greater than 500 Ohm*cm, such as around 1 kOhm*cm. In certain embodiments, one or more of the bipolar devices are surrounded by a low-resistivity implant configured to reduce effects of harmonic and other interference.

Abstract: A lead frame includes: a resin portion including an upper surface and a lower surface opposite to the upper surface; and a first terminal formed to penetrate the resin portion. The first terminal includes: a first upper terminal portion disposed to protrude from the upper surface; a first lower terminal portion disposed on the first upper terminal portion to protrude from the lower surface; a first through hole formed in one of the first upper terminal portion and the first lower terminal portion; a first recess defined by an inner wall surface of the first through hole and a surface of the other of the first upper terminal portion and the first lower terminal portion; and a first metal layer formed on an inner surface of the first recess.

Abstract: A semiconductor memory device according to an embodiment includes: a first wiring line extending in a first direction; a second wiring line extending in a second direction, the second direction intersecting the first direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a channel body disposed at a first end of the first wiring line; a third wiring line electrically connected to the first wiring line via the channel body; and a gate wiring line extending in the first direction and facing the channel body from the second direction.

Abstract: A spacer structure and a fabrication method thereof are provided. The method includes the following operations. First and second conductive structures are formed over a substrate. Dielectric layer is formed to cover the first and second conductive structures. Hard mask layer is formed over the dielectric layer. The hard mask layer covers the dielectric layer over the first conductive structure, and the hard mask layer has an opening exposing the dielectric layer over the second conductive structure. The dielectric layer exposed by the hard mask layer is etched to reduce thickness of the dielectric layer. The hard mask layer is removed. The dielectric layer is etched to form first main spacer on sidewall of the first conductive structure and second main spacer on sidewall of the second conductive structure. A first width of the first main spacer is greater than a second width of the second main spacer.

Abstract: A crystal orientation layer laminated structure capable of widely selecting materials for a base substrate and an electrode substrate, an electronic memory using the crystal orientation layer laminated structure and a method for manufacturing the crystal orientation layer laminated structure are provided. The crystal orientation layer laminated structure according to the present invention has such a feature as including a substrate, including an orientation control layer which is laminated on the substrate, which is made of any of germanium, silicon, tungsten, germanium-silicon, germanium-tungsten and silicon-tungsten, and whose thickness is at least 1 nm or more, and including a first crystal orientation layer which is laminated on the orientation control layer, which is made of any of SbTe, Sb2Te3, BiTe, Bi2Te3, BiSe and Bi2Se3 as a main component, and which is oriented in a certain crystal orientation.

Abstract: A power electronics assembly includes a semiconductor device, a metal substrate, and a cooling structure. The metal substrate includes a plurality of stress-relief features that extend at least partially through a thickness of the metal substrate. The plurality of stress-relief features are at least partially filled with a transient liquid phase (TLP) bonding material. The semiconductor device is positioned over the plurality of stress-relief features and thermally bonded to the metal substrate via TLP bonding material. Vehicles having power electronics assemblies with stress-relief through-features are also disclosed.

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

Abstract: When a channel formation region is formed of GaN in a MOSFET, there are cases where the actual threshold voltage (Vth) is lower than the setting value thereof and the actual carrier mobility (?) during the ON state is lower than the setting value thereof. The reason for threshold voltage (Vth) and the carrier mobility (?) being lower than the setting values is unknown. A MOSFET including a gallium nitride substrate, an epitaxial layer made of gallium nitride provided on top of the gallium nitride substrate, a gate insulating film provided in direct contact with the epitaxial layer, and a gate electrode provided in contact with the gate insulating film. The gallium nitride substrate has a dislocation density less than or equal to 1E+6 cm?2, and the epitaxial layer has a region with a p-type impurity concentration less than or equal to 5E+17 cm?3.

Abstract: A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.