Patents Examined by Michael Sun
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Patent number: 11966344Abstract: An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.Type: GrantFiled: July 28, 2022Date of Patent: April 23, 2024Assignees: Samsung Electronics Co., Ltd., SNU R&DB FOUNDATIONInventors: Seung Wook Lee, Hweesoo Kim, Jung Ho Ahn
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Patent number: 11940938Abstract: A hypervisor is configured to bridge I/O operations between the NVMeoPCIe version of the NVMe I/O protocol and the NVMeoF version of the NVMe I/O protocol. By providing a bridging hypervisor, guests can use the NVMePCIe version of the NVMe I/O protocol for storage access operations, while the hypervisor can use the NVMeoF version of the NVMe I/O protocol to implement the storage access operations on attached storage resources of the storage system. The hypervisor handles administrative actions associated with creating, managing, and destroying submission queues and completion queues. Once the desired queue configuration has been created, NVMeoPCIe I/O operations are able to be transparently bridged by the hypervisor, which greatly reduces the amount of processing that would be required if the hypervisor were required to terminate each NVMeoPCIe I/O operation, generate corresponding NVMeoF I/O operations, and keep track of each such pair of I/O operations.Type: GrantFiled: July 1, 2022Date of Patent: March 26, 2024Assignee: Dell Products, L.P.Inventor: Matthew H. Fredette
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Patent number: 11934836Abstract: A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.Type: GrantFiled: August 15, 2022Date of Patent: March 19, 2024Assignee: Lodestar Licensing Group LLCInventor: Steven Jeffrey Wallach
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Patent number: 11935600Abstract: Devices and techniques for programmable atomic operator resource locking are described herein. A request for a programmable atomic operator (PAO) can be received at a memory controller that includes a programmable atomic unit (PAU). Here, the request includes an identifier for the PAO and a memory address. The memory addressed is processed to identify a lock value. A verification can be performed to determine that the lock value indicates that there is no lock corresponding to the memory address. Then, the lock value is set to indicate that there is now a lock corresponding to the memory address and the PAO is invoked based on the identifier for the PAO. In response to completion of the PAO, the lock value is set to indicate that there is no longer a lock corresponding to the memory address.Type: GrantFiled: March 6, 2023Date of Patent: March 19, 2024Assignee: Micron Technology, Inc.Inventor: Tony Brewer
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Patent number: 11928469Abstract: A neural network operation apparatus and method are disclosed. The neural network operation apparatus may include an adder configured to perform addition of data for performing a neural network operation and main data, a first multiplexer configured to output one of an output result of the adder and the main data based on a reset signal, a second multiplexer configured to output one of the main data and a quantization result of the data based on a phase signal, and a controller configured to control the first and second multiplexers by generating the reset signal and the phase signal.Type: GrantFiled: July 13, 2022Date of Patent: March 12, 2024Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB FoundationInventors: Hanwoong Jung, Soonhoi Ha, Donghyun Kang, Duseok Kang
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Patent number: 11914531Abstract: A host controller interface configured to provide interfacing between a host device and a storage device includes processing circuitry; a doorbell register configured to store a head pointer and a tail pointer of one or more first queues; and an entry buffer configured to store a first command from one of the one or more first queues in the entry buffer, wherein the processing circuitry is configured to, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues.Type: GrantFiled: December 9, 2022Date of Patent: February 27, 2024Assignee: Samsung Electronics Co., LtdInventors: Myungsub Shin, Sungho Seo, Kwanwoo Noh, Seongyong Jang, Haesung Jung
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Patent number: 11907721Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a pad value indicator. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. A padded stream vector is formed that includes a specified pad value without accessing the pad value from system memory.Type: GrantFiled: July 19, 2021Date of Patent: February 20, 2024Assignee: Texas Instruments IncorporatedInventors: Asheesh Bhardwaj, Timothy David Anderson, Son Hung Tran
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Patent number: 11886874Abstract: An arithmetic operation device causes a convolution arithmetic unit to perform a convolution arithmetic operation between a filter and target data corresponding to a size of the filter in each of a plurality of convolution layers constituting a neural network. The arithmetic operation device includes: a bit reduction unit that reduces a bit string corresponding to a first bit number from a least significant bit of the target data and reduces a bit string corresponding to a second bit number from a least significant bit of a weight that is an element of the filter for each convolution layer; and a bit addition unit that adds a bit string corresponding to a third bit number obtained by adding the first bit number and the second bit number to a least significant bit of a convolution arithmetic operation result output from the convolution arithmetic unit by inputting the target data and the weight after being reduced by the bit reduction unit to the convolution arithmetic unit.Type: GrantFiled: April 8, 2020Date of Patent: January 30, 2024Assignee: HITACHI ASTEMO, LTD.Inventors: Tadashi Kishimoto, Goichi Ono, Akira Kitayama, Daichi Murata
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Patent number: 11880315Abstract: An example peripheral device includes circuitry to identify a target device that matches the device type identifier of the peripheral device. The example circuitry of the peripheral device is to cause selection of an input component device, transmission of a request to place the input component of the target device into an instruction set receiver mode, and operation of an output component of the peripheral device to produce audio output or video output that represents the instruction set in response to a determination that an instruction set version identifier of the target device mismatches the instruction set version identifier of the peripheral device.Type: GrantFiled: April 15, 2020Date of Patent: January 23, 2024Assignee: Hewlett-Packard Development Company, L.P.Inventors: John Frederick, Timothy Paul Guynes, Anthony Kaplanis, Syed S. Azam
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Patent number: 11870829Abstract: Methods and systems for transmitting data are presented. Data received from at least one data source is retained in at least one buffer. In one example, initial hierarchical data may be provided from the at least one buffer to a device, followed by additional hierarchical data. In one example, the data is received into the at least one buffer via a multicast connection, and the data is provided to the device via a point-to-point connection.Type: GrantFiled: March 11, 2022Date of Patent: January 9, 2024Assignee: OPENTV, INC.Inventor: John Tinsman
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Patent number: 11868292Abstract: A plurality of resource requesters may be configured to consume a resource to perform a task. Each of the plurality of resource requesters can be allocated a resource budget to consume the resource to perform the task. An arbiter can select one of the plurality of resource requesters to consume the resource based on an arbitration scheme. When a resource requester is selected, the amount of resource consumed by the resource requester can be deducted from its resource budget. When the resource requester is idle for a number of cycles when selected, the corresponding resource budget can be further reduced to account for the actual amount of resource consumed and wasted by the resource requester, which can provide fairness in resource consumption over few rounds of arbitration.Type: GrantFiled: March 28, 2022Date of Patent: January 9, 2024Assignee: Amazon Technologies, Inc.Inventors: Lev Vaskevich, Noam Katz
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Patent number: 11861656Abstract: A disclosed example apparatus to monitor a media device includes: an input to obtain a signal at a universal serial bus port of the media device; and a bit rate comparator to: determine the media device is involved in a data transfer if a bit rate of the signal exceeds a threshold; and determine the media device is not involved in the data transfer if the bit rate of the signal does not exceed the threshold.Type: GrantFiled: October 24, 2022Date of Patent: January 2, 2024Assignee: The Nielsen Company (US), LLCInventors: Mark Cave, Joseph Volpatti
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Patent number: 11861398Abstract: Method and apparatuses for communicating instruction data items from a control apparatus to a device to be controlled are disclosed. The control apparatus receives a request for at least one instruction data item from a device and responds the request by sending a response message. The responding comprises selectively including at least one instruction data item in the response message based at least partly on determination whether the requested at least one data item has been sent before.Type: GrantFiled: December 27, 2021Date of Patent: January 2, 2024Assignee: NOKIA TECHNOLOGIES OYInventor: Arto Kristian Suvitie
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Patent number: 11861218Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.Type: GrantFiled: November 7, 2022Date of Patent: January 2, 2024Assignee: KIOXIA CORPORATIONInventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
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Patent number: 11853242Abstract: Provided are a synchronization control method, a chip, an electronic device and a storage medium. A master device sets a reference time for a plurality of slave devices wirelessly connected to the master device; and determines a target count value K of a connection event and an offset time of a respective slave device for each of the plurality of slave devices. The master device transmits the target count value of the connection event and the offset time to the respective slave device, so that each of the plurality of slave devices performs control based on the target count value of the connection event and the offset time of the respective slave device, so as to perform a task at the reference time.Type: GrantFiled: December 27, 2021Date of Patent: December 26, 2023Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.Inventors: Chuan Pu, Dingfu Lian
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Patent number: 11847071Abstract: Enabling communication between multiple storage controllers and a single-ported storage device, including determining, by an arbiter, that a first storage system controller of a plurality of storage system controllers has gained exclusive access to a single-ported storage device having a plurality of lanes; and in response to the determination, enabling communication between the first storage system controller and the storage device; and preventing communication between the storage device and at least one other storage system controller of the plurality of storage system controllers.Type: GrantFiled: December 30, 2021Date of Patent: December 19, 2023Assignee: PURE STORAGE, INC.Inventor: Peter Kirkpatrick
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Patent number: 11842436Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.Type: GrantFiled: August 1, 2022Date of Patent: December 12, 2023Assignee: Apple Inc.Inventors: Winnie W. Yeung, Leela Kishore Kothamasu, Zelin Zhang, Guanlan Xu, Eddie M. Robinson
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Patent number: 11841808Abstract: A method, computer program product, and computing system for associating a plurality of NVMe IO submission queues with an NVMe IO completion queue. An NVMe IO completion queue polling frequency may be defined for a plurality of threads configured to provide one or more IO requests to the plurality of NVMe IO submission queues. The NVMe IO completion queue may be polled based upon, at least in part, the NVMe IO completion queue polling frequency defined for the plurality of threads.Type: GrantFiled: July 14, 2021Date of Patent: December 12, 2023Assignee: EMC IP Holding Company, LLCInventors: Eldad Zinger, Leonid Ravich, Elad Grupi
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Patent number: 11835993Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.Type: GrantFiled: March 6, 2023Date of Patent: December 5, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: DongSik Cho, Jeonghoon Kim, Rohitaswa Bhattacharya, Jaeshin Lee, Honggi Jeong
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Patent number: 11829769Abstract: Systems and/or methods can include techniques to exploit dynamic timing slack on the chip. By using a special clock generator, the clock period can be shrunk as needed at every cycle. The clock period is determined during operation by checking “critical path messengers” to indicate how much dynamic timing slack exists. Elastic pipeline timing can also be introduced to redistribute timing among pipeline stages to bring further benefits.Type: GrantFiled: December 18, 2019Date of Patent: November 28, 2023Assignee: NORTHWESTERN UNIVERSITYInventors: Jie Gu, Russell E. Joseph