Abstract: A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier; sensing a first response; determining a reference signal based on the first signal; sensing a second response based on a second signal that is determined based on the first signal; and determining the state of the memory cell based on the second response and the reference signal. Also, a memory device that is able to determine the state of the memory cell is provided.

Abstract: A memory system includes a nonvolatile memory having a plurality of blocks, and a memory controller. The memory controller is configured to control the nonvolatile memory, record an association between a first stream ID and a first block in which first data corresponding to the first stream ID is written, collect information on the first data written into the first block, and invalidate the association between the first stream ID and the first block based on the collected information.

Abstract: Semiconductor memory devices and methods for writing data in memory cells are provided. An exemplary method for writing data in a memory cell includes providing the memory cell with a first pull-up transistor, a first power supply line coupled to the first pull-up transistor, a second pull-up transistor, and a second power supply line coupled to the second pull-up transistor. The method further includes applying a primary voltage from the first power supply line to the first pull-up transistor. The method also includes applying a secondary voltage from the second power supply line to the second pull-up transistor, wherein the secondary voltage is higher than the primary voltage. Further, the method includes performing a write operation to save a selected value in the memory cell.

Abstract: A memory system includes a semiconductor memory and a controller. The controller is configured to perform a read operation on the semiconductor memory in response to a read instruction received from a host. In response to the read instruction that includes a first logical address, the controller converts the first logical address into a first physical address, and issues a read command and a second physical address different from the first physical address, to the semiconductor memory.

Abstract: A flash memory controller is configured to hold a read pattern defining an order of selection of read options specifying a parameter value for a read from the flash memory chip. The flash memory controller is configured to execute error correction on data read from the flash memory chip in accordance with the read command. The flash memory controller is configured to designate a next read option specified in the read pattern to read the data from the flash memory chip in a case where all errors in the read data are not corrected by the error correction.

Abstract: An apparatus of a memory system and an operating method thereof include: memory blocks, each of the memory blocks includes strings, each of the stings has flash cells and select gates thereon, wherein the select gates of each of the strings with a same index number in each of the memory blocks are connected with each other, in each of the memory blocks, the strings are divided into groups, each of the groups includes at least one string, and each of the groups has own read counts management thereof.

Abstract: A method of programming electrical fuses reliably is disclosed. If a programming current exceeds a critical current, disruptive mechanisms such as rupture, thermal runaway, decomposition, or melt, can be a dominant programming mechanism such that programming is not be very reliable. Advantageously, by controlled programming where programming current is maintained below the critical current, electromigration can be the sole programming mechanism and, as a result, programming can be deterministic and very reliable. In this method, fuses can be programmed in multiple shots with progressive resistance changes to determine a lower bound that all fuses can be programmed satisfactorily and an upper bound that at least one fuse can be determined failed. If programming within the lower and upper bounds, defects due to programming can be almost zero and, therefore, defects are essentially determined by pre-program defects.

Abstract: A computer program product according to one embodiment includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processing circuit to cause the circuitry to perform a method including determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values for the data written to the non-volatile memory block are calculated, the values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The overall threshold voltage shift values are stored. A base threshold voltage shift (TVSBASE) value, the one or more TVS? values, or both the TVSBASE value and the one or more TVS? values are re-calibrated during a background health check after a predetermined number of background health checks without calibration are performed.

Abstract: In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processing circuit to cause the processing circuit to perform a method that includes determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block. The one or more overall threshold voltage shift values are stored. The method also includes reading one or more TVS values from a non-volatile controller memory, and resetting a program/erase cycle count since last calibration after calibrating the one or more overall threshold voltage shift values. The one or more TVS? values and the program/erase cycle count since last calibration are stored to the non-volatile controller memory.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include a free layer including a plurality of magnetic layers each having a variable magnetization direction; a tunnel barrier layer formed over the free layer; and a pinned layer formed over the tunnel barrier layer and having a pinned magnetization direction; wherein the plurality of magnetic layers in the free layer includes a first magnetic layer in contact with the tunnel barrier layer and a second magnetic layer not in contact with the tunnel barrier layer and a sum of an exchange field between the first magnetic layer and the second magnetic layer and a stray field generated by the first magnetic layer is larger than or the same as a difference between a uniaxial anisotropy field of the second magnetic layer and a demagnetizing field due to a shape of the second magnetic layer.

Abstract: An integrated optical circuit for holographic information processing is disclosed. The optical circuit comprises a photorefractive medium and two transmitter arrays. The transmitter arrays are adapted for locally changing the refractive index of the photorefractive medium for holographic encoding of the information in a working plane of the photorefractive medium by transmitting light via optical paths into the photorefractive medium such that an interference pattern is generated in the working plane. The optical paths and the working plane are arranged in a single optical plane.

Abstract: An operating method of a nonvolatile memory device includes storing different data in first and second reference cells connected to a word line, checking whether the different data are abnormally stored in the first and second reference cells, and when it is determined that the different data are abnormally stored in the first and second reference cells, swapping the first and second reference cells.

Abstract: A semiconductor device may be provided. The semiconductor device may operate in a 2N mode as well as a normal mode.

Abstract: A semiconductor memory device and a reading method thereof are provided. A flash memory includes a memory cell array; a page buffer/reading circuit, holding data of a selected page of the memory cell array; a decoding/selecting circuit, selecting n bits data from the data held by the page buffer based on a column address; and a data bus for n bits, which is connected to the decoding/selecting circuit. The decoding/selecting circuit further connects n/2 bits data of an even address to a lower bit position of the data bus and connects n/2 bits data of an odd address to a upper bit position of the data bus based on the column address. When the start address is the odd address, data of the odd address and data of the even address next to the odd address are selected.

Abstract: A nonvolatile memory device includes a memory cell array, a row decoder circuit, a page buffer circuit, and a control logic circuit. The control logic circuit controls the row decoder circuit and the page buffer circuit to perform: (1) a pre-program of sequentially selecting a plurality of memory blocks and increasing threshold voltages of string selection transistors or ground selection transistors of the selected memory block and (2) after the pre-program is completed, a main program of sequentially selecting the plurality of memory blocks, programming string selection transistors or ground selection transistors of the selected memory block, and performing a verification by using a verification voltage.

Abstract: A data receiver for a double data rate (DDR) memory includes a first stage circuit and a second stage circuit. The first stage circuit is deployed for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals. The second stage circuit, coupled to the first stage circuit, is deployed for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal. Both of the first stage circuit and the second stage circuit are implemented in a core voltage domain.

Abstract: A device includes a memory bit cell and a retention circuit. The memory bit cell includes a first metal line and a second metal line. The first metal line is disposed in a first metal layer and configured to receive a retention voltage. The second metal line is disposed in the first metal layer and configured to receive a first reference voltage lower than the retention voltage. The retention circuit includes a third metal line. The third metal line is disposed in the first metal layer and configured to transmit the retention voltage to the first metal line. A distance between the second metal line and the third metal line is less than a length of the memory bit cell.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of the memory cell may be initialized to a value associated with the threshold voltage of a switching component in electronic communication with the memory cell. The voltage may be initialized by reducing the existing voltage on the access line to the value. The switching component or an additional pull down device, or both, may be used to reduce the voltage of the access line. After the access line has been initialized to the value, the read operation may be triggered.

Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a reset signal, command/address signals and data. The second semiconductor device may be configured to generate internal commands, internal addresses and internal data for performing an initialization operation. The second semiconductor device may be configured to store the internal data in a plurality of memory cells selected by the internal commands and the internal addresses.