Abstract: Embodiments are directed to optimizing data transfers between heterogeneous memory arenas. In one scenario, a computer system receives an indication that a data chunk is to be transferred from a first memory arena to a third memory arena, and then determines that for the data chunk to be transferred from the first memory arena to the third arena, the data chunk is to be transferred from the first memory arena to a second memory arena, and from the second memory arena to the third memory arena. The computer system divides the data chunk into smaller data portions and copies a first data portion from the first memory arena to the second memory arena. The computer system then copies the first data portion from the second memory arena to the third memory arena and copies a second data portion from the first memory arena to the second memory arena in parallel.

Abstract: A method includes sending a first signal from a memory device to a memory controller. The first signal indicates to the memory controller that particular memory cells of the memory device are to be refreshed by the memory device.

Abstract: A method and system are disclosed that monitor and control random cache read operations. Random cache read operation may occur until the expiration of a timer. Upon expiration of the timer, the current random cache read sequence is terminated and new received read commands will not use this sequence. A flash controller may either use a page read operation or initiate a new random cache read sequence.

Abstract: Methods and systems are described herein to provide efficient data retrieval in a data storage system. Specifically, in cases where users of a data storage system are not overly sensitive to data retrieval time, such as the case for backup and archival data storage systems, random read requests may be fulfilled as part of sequential reads to reduce I/O operations. A data storage system may be divided into data storage zones. Sequential reads may be performed for data stored in those data storage zones with pending data retrieval requests. Data retrieval requests may be fulfilled based at least in part on the sequentially-read data.

Abstract: A cache device may include a first cache including a first set and a plurality of ways corresponding to the first set, and a second cache including a second set and a plurality of ways corresponding to the second set. The second set is related with the first set depending on a vacancy of the ways of the first set.

Abstract: An arithmetic processing device includes a decoder which decodes commands, a command holding unit configured to register therein the commands involving memory accesses among the decoded commands, a hardware prefetch controller configured to execute a prefetch in response to a trigger independent of a prefetch command to execute the prefetch, the prefetch being an operation of transferring data stored in a memory to a cache memory in advance, and a controller configured to determine whether an unnecessary prefetch command to transfer the data, which is to be transferred to the cache memory by the hardware prefetch controller, from the memory to the cache memory is registered in the command holding unit, and disables the unnecessary prefetch command when the unnecessary prefetch command is registered in the command holding unit.

Abstract: Embodiments relate to managing memory page tables in a processing system. A request to access a desired block of memory is received. The request includes an effective address that includes an effective segment identifier (ESID) and a linear address, the linear address including a most significant portion and a byte index. An entry in a buffer that includes the ESID of the effective address is located. Based on the entry including a radix page table pointer (RPTP), performing: using the RPTP to locate a translation table of a hierarchy of translation tables, using the located translation table to translate the most significant portion of the linear address to obtain an address of a block of memory, and based on the obtained address, performing the requested access to the desired block of memory.

Abstract: A method includes receiving a request to access a desired block of memory. The request includes an effective address that includes an effective segment identifier (ESID) and a linear address, the linear address comprising a most significant portion and a byte index. Locating an entry, in a buffer, the entry including the ESID of the effective address. Based on the entry including a radix page table pointer (RPTP), performing, using the RPTP to locate a translation table of a hierarchy of translation tables, using the located translation table to translate the most significant portion of the linear address to obtain an address of a block of memory, and based on the obtained address, performing the requested access to the desired block of memory.

Abstract: Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

Abstract: A method for collection instance resizing. The method may include identifying at least one collection object within a collection framework of a virtual machine. The method may also include determining the at least one identified collection object satisfies at least one preconfigured criteria. The method may further include determining a garbage collection cycle count associated with the at least one identified collection object exceeds a preconfigured threshold. The method may also include determining an occupancy ratio associated with the at least one identified collection object is less than a preconfigured shrink threshold. The method may further include restructuring the at least one identified collection object based on the at least one identified collection object satisfying the at least one preconfigured criteria, the garbage collection cycle count exceeding the preconfigured threshold, and the occupancy ratio being less than the preconfigured shrink threshold.

Abstract: Techniques are described herein which minimize the impact of virtual machine snapshots on the performance virtual machines and hypervisors. In the context of a volume snapshot which may involve (i) taking virtual machine snapshots of all virtual machines associated with the volume, (ii) taking the volume snapshot, and (iii) removing all the virtual machine snapshots, the virtual machine snapshots may be created in a first order and removed in a second order. Specifically, snapshots for busy virtual machines (i.e., virtual machines with higher disk write activity) may be created last and removed first. Consequently, snapshots of busy virtual machines are retained for shorter periods of time, thereby minimizing the effect of virtual machine snapshots on those virtual machines (and their associated hypervisors) that would be most negatively impacted by virtual machine snapshots.

Abstract: Storing data from a volatile memory of a host in a non-volatile memory (NVM) of a data storage device (DSD). Data from the volatile memory of the host is identified which has been compressed with a first compression ratio. The identified data is decompressed and a second compression ratio is determined based on a time to restore the data to the volatile memory of the host and characteristics of the NVM. At least a portion of the decompressed data is recompressed with the second compression ratio and at least a portion of the recompressed data is stored in the NVM.

Abstract: The invention provides a technique for managing write operations issued to a non-volatile memory included in a wireless device. A monitor software application executes on the wireless device and is configured to determine that a number of write operations issued to the non-volatile memory is greater than or equal to a write operation threshold associated with the non-volatile memory. In response, at least one application is isolated as the application responsible for issuing excessive write operations. The isolation can be carried out locally on the wireless device, or the isolation can be carried out remotely at a server by sending information about the write operations to the server. The monitor then limits additional write operations from being issued to the non-volatile memory so as to protect the non-volatile memory from becoming corrupted or inoperable.

Abstract: A method for collection instance resizing. The method may include identifying at least one collection object within a collection framework of a virtual machine. The method may also include determining the at least one identified collection object satisfies at least one preconfigured criteria. The method may further include determining a garbage collection cycle count associated with the at least one identified collection object exceeds a preconfigured threshold. The method may also include determining an occupancy ratio associated with the at least one identified collection object is less than a preconfigured shrink threshold. The method may further include restructuring the at least one identified collection object based on the at least one identified collection object satisfying the at least one preconfigured criteria, the garbage collection cycle count exceeding the preconfigured threshold, and the occupancy ratio being less than the preconfigured shrink threshold.

Abstract: Disclosed are a method and device for implementing memory migration, which relate to computer technology and are invented for solving the problem that the existing operating process for memory migration is relatively complicated. The technical solution provided in the embodiments of the present application includes: the basic input-output system of a computer migrating the data in the memory to be migrated to a first unavailable memory in the operating system of the computer when migrating the memory to be migrated and the basic input-output system storing the mapping relationship between the memory to be migrated and the physical address of the first unavailable memory. The embodiments of the present application can be applied to ordinary computer systems and computer systems under the NUMA architecture.

Abstract: A method for collection instance resizing. The method may include identifying at least one collection object within a collection framework of a virtual machine. The method may also include determining the at least one identified collection object satisfies at least one preconfigured criteria. The method may further include determining a garbage collection cycle count associated with the at least one identified collection object exceeds a preconfigured threshold. The method may also include determining an occupancy ratio associated with the at least one identified collection object is less than a preconfigured shrink threshold. The method may further include restructuring the at least one identified collection object based on the at least one identified collection object satisfying the at least one preconfigured criteria, the garbage collection cycle count exceeding the preconfigured threshold, and the occupancy ratio being less than the preconfigured shrink threshold.

Abstract: Techniques are described herein which minimize the impact of virtual machine snapshots on the performance virtual machines and hypervisors. In the context of a volume snapshot which may involve (i) taking virtual machine snapshots of all virtual machines associated with the volume, (ii) taking the volume snapshot, and (iii) removing all the virtual machine snapshots, the virtual machine snapshots may be created in a first order and removed in a second order. Specifically, snapshots for busy virtual machines (i.e., virtual machines with higher disk write activity) may be created last and removed first. Consequently, snapshots of busy virtual machines are retained for the shorter periods of time, thereby minimizing the effect of virtual machine snapshots on those virtual machines (and their associated hypervisors) that would be most negatively impacted by virtual machine snapshots.

Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in the platform storage hierarchy. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM is coupled to the processor to be directly accessed by the processor without going through an I/O subsystem. The NVRAM stores a Basic Input and Output System (BIOS). During a Pre-Extensible Firmware Interface (PEI) phase of the boot process, the cache within the processor can be used in a write-back mode for execution of the BIOS.

Abstract: A system and method is provided for parallel processing of multiple write requests to write data associated the multiple write requests to a storage area concurrently. The file system receives a series of write request from one more applications executing on the computing device. The file system includes one or more processing modules that selectively groups writes request into lists or trains. After the processing modules begin processing first threads associated with writes in a first train, the processing modules determines whether and when to initiate processing of second threads associated with writes in a second train during processing of the first threads.

Abstract: A network unit, comprising a processor and a random access memory (RAM) component coupled to the processor, wherein the RAM component comprises a memory management unit (MMU) and a data RAM, wherein the MMU comprises a complete page address table for translating a virtual memory address received from the processor into a physical memory address, and wherein the complete page address table is substantially static.