Abstract: A nonvolatile memory with NAND structured cells includes a plurality of cell units formed of a plurality of series-connected memory transistors, each having a source, a drain, a floating gate and a control gate. A row decoder is connected to the control gates of each memory transistor selects at east one of the cell units and one of the memory transistors within the selected cell unit. During programming, the row decoder causes a different pass potential to be applied to nonselected word lines adjacent to selected word lines than that which is applied to other nonselected word lines. Adjacent memory transistors respectively connected to the drain and source of the selected memory transistor on an unselected bit line are thus rendered nonconductive. Thereafter, the selected memory transistor is charged to a local boost potential when a programming potential is applied thereto, and a variation of its threshold voltage is prevented.