Patents Examined by Midys Rojas
  • Patent number: 11966616
    Abstract: A current value for a reference voltage for a block family is determined. An amount of voltage shift for a memory page of the block family is determined based on the current value for the reference voltage and a prior value for the reference voltage. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: April 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Mustafa N. Kaynak, Peter Feeley, Sivagnanam Parthasarathy, Sampath Ratnam, Shane Nowell
  • Patent number: 11966598
    Abstract: Indices of storage systems are managed. An example method includes: receiving a flush cycle for flushing expired events in a storage system including multiple events in a data stream, determining, based on the flush cycle, a time slice for managing the index of the storage system, creating a slice index node for the time slice in response to determining that the occurrence time of a first event that enters the storage system in the data stream is within the time slice, wherein the slice index node includes an index node of the first event, and adding the slice index node to the index. A corresponding device and a corresponding computer program product are provided. Thus, the index of a large number of events entering the storage system is managed according to the occurrence time of the events, and the storage system can be searched and updated accurately and effectively.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: April 23, 2024
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Julius Jian Zhu, Lu Lei, Pengfei Su, Jingjing Liu
  • Patent number: 11954340
    Abstract: Disclosed is a nonvolatile memory, which includes a plurality of input/output pads connectable to a plurality of data lines, an enable input pad, an enable output pad, and a chip address initialization circuit. The chip address initialization circuit receives a current chip address through the plurality of input/output pads, stores the current chip address in response to a current enable signal received through the enable input pad, outputs a next enable signal through the enable output pad, and outputs a next chip address through the plurality of input/output pads.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: April 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Bong-Kil Jung
  • Patent number: 11954368
    Abstract: According to one embodiment, a memory system includes a communication interface connectable to a plurality of hosts. A virtual controller creation unit creates a virtual controller based on connection of a host to the communication interface. An access management unit manages permission information indicating a correspondence between each of the plurality of namespaces and a host permitted to access the namespace. The virtual controller creation unit create, based on the permission information, a first virtual controller to which a namespace that a first host connected to the communication interface is permitted to access is attached, as a virtual controller to be used by the first host to access a nonvolatile memory.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: April 9, 2024
    Assignee: Kioxia Corporation
    Inventor: Tatsuya Sasaki
  • Patent number: 11928356
    Abstract: Methods, systems, and apparatuses related to source address memory management are described. For example, a controller can be coupled to a memory device to select a source block, a destination block, and a metadata block. The controller can store metadata indicative of an address of the source block in the metadata block. The controller can perform a memory management operation to transfer data from the source block to the destination block.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Jianmin Huang, Xiaolai Zhu
  • Patent number: 11922051
    Abstract: A system for an artificial neural network (ANN) includes a processor configured to output a memory control signal including an ANN data locality; a main memory in which data of an ANN model corresponding to the ANN data locality is stored; and a memory controller configured to receive the memory control signal from the processor and to control the main memory based on the memory control signal. The memory controller may be further configured to control, based on the memory control signal, a read or write operation of data of the main memory required for operation of the artificial neural network. Thus, the system optimizes an ANN operation of the processor by utilizing the ANN data locality of the ANN model, which operates at a processor-memory level.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 5, 2024
    Assignee: DEEPX CO., LTD.
    Inventor: Lok Won Kim
  • Patent number: 11922013
    Abstract: A method for contention reduced update of one or more storage system parameters, the method may include (i) concurrently monitoring the one or more storage system parameters (SSPs) by compute entities (CEs); wherein the concurrently monitoring comprises updating, by the CEs, local counters allocated to different SSPs; (ii) updating, by the CEs, sets of shared counter fields with values of the local counters, wherein different sets are allocated to different SSPs; wherein an updating of a set of a shared counter fields by an CE comprises selecting a shared counter field of the set by the CE; and (iii) calculating values of the different SSPs, wherein a calculating of a value of a SSP is based on at least one value of at least one shared counter field of a set that is allocated to the SSP.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: March 5, 2024
    Assignee: VAST DATA LTD.
    Inventors: Amir Miron, Avi Goren
  • Patent number: 11893143
    Abstract: A storage device for data encryption and self-destruction includes a controller, an interface module, a storage module, an encryption and authentication module, a positioning module, a power supply module, and a communication and self-destruction module. The interface module, the storage module, the encryption and authentication module, the positioning module and the communication and self-destruction module are electrically connected to the controller, respectively. The encryption and authentication module is configured to encrypt and protect data stored in the storage module, and authenticate a request for remote access to the storage device. The communication and self-destruction module is configured to send position information acquired by the positioning module to a storage device management system, receive and execute a data destruction instruction issued by the storage device management system, and destruct the data stored in the storage module.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: February 6, 2024
    Assignee: Hainan University
    Inventors: Chunjie Cao, Xin Zheng, Yang Sun, Fangjian Tao
  • Patent number: 11893264
    Abstract: Systems and methods are described for efficiently processing events related to a relationship between a primary copy of data at a primary storage system and a mirror copy of the data at a cross-site secondary storage system of a multi-site distributed storage system. According to an example, a mediator agent that is configured on both primary and secondary storage systems provides coordination and serialization for various events generated in the relationship. The multi-site distributed storage system performs actions based on the event processing such as performing a failover operation from the primary storage system to the secondary storage system or resynchronizing the relationship to ensure application protection and availability.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: February 6, 2024
    Assignee: NetApp, Inc.
    Inventors: Anoop Vijayan, Akhil Kaushik, Sohan Shetty, Dhruvil Shah
  • Patent number: 11886719
    Abstract: A memory circuit for storing parsimonious data and intended to receive an input vector of size Iz, includes an encoder, a memory block comprising a first memory region and a second memory region divided into a number Iz of FIFO memories, each FIFO memory being associated with one component of the input vector, only non-zero data being saved in the FIFO memories, a decoder, the encoder being configured to generate an indicator of non-zero data for each component of the input vector, the memory circuit being configured to write the non-zero data of the input data vector to the respective FIFO memories and to write the indicator of non-zero data to the first memory region, the decoder being configured to read the outputs of the FIFO memories and the associated indicator in the first memory region.
    Type: Grant
    Filed: June 18, 2022
    Date of Patent: January 30, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Vincent Lorrain, Olivier Bichler, David Briand, Johannes Christian Thiele
  • Patent number: 11886723
    Abstract: According to some embodiments, a system, method and non-transitory, computer readable medium are provided comprising a memory storing processor-executable program code; and a processing unit to cause the system to: receive a range of persistent volume disk size values from a cloud service provider; receive a value for an upper bound of a number of persistent volume disks attachable to a virtual machine per the cloud service; determine a number of persistent volume disks based on the upper bound, wherein the number is at least two; generate a plurality of configurations of the determined number of persistent volume disks, wherein a configuration is provided for each persistent volume disk size value, and each configuration divides the persistent volume disk size value between two or more persistent volume disks; and aggregate the generated plurality of configurations in a decision table. Numerous other aspects are provided.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: January 30, 2024
    Assignee: SAP SE
    Inventors: Prateek Agarwal, Paresh Rathod, Samar Desai, Shrikant Awate, Amit Pathak, Dheren Gala, Mitali Yadav
  • Patent number: 11886721
    Abstract: A method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, a gate voltage of the transistor, and an actual time at which data is written into the memory; acquiring a current temperature of the transistor; and adjusting the gate voltage, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted gate voltage is within a preset writing time.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: January 30, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shu-Liang Ning
  • Patent number: 11880586
    Abstract: Aspects of the present disclosure relate to enabling storage array-based remote replication from containerized applications operating on one or more node clusters. In embodiments, a host executing one or more operations from a node cluster is provided an interface (e.g., an application programming interface (API)) to a storage array. Additionally, the host can be delivered resources to manage and monitor the storage array to perform one or more data replication services directly from the node cluster and via the interface. Further, data replications services are triggered in response to instructions issued by the host directly from the node cluster and via the interface.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: January 23, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Utkarsh Dubey, Numan Elahi Tramboo, Prasant Kumar Padhi, Thomas Watson
  • Patent number: 11875050
    Abstract: Provided herein is a memory device including a memory block with memory cells to which word lines and bit lines are connected; page buffers, connected to the memory block through the bit lines, during a program operation, configured to convert original data that is received from an external device into variable data that is divided into groups according to a number of specific data, and configured to apply a program enable voltage or a program inhibit voltage to the bit lines according to the variable data; and a data pattern manager configured to control the page buffers to convert the original data into the variable data during the program operation.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: January 16, 2024
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Patent number: 11868649
    Abstract: Methods, systems, and devices for memory systems for secure sequential storage devices are described. The system may identify a request for a first portion of a memory system to operate in a first configuration and a second portion of the memory system to operate in a second configuration. The system may enter, a first power mode having a lower power consumption than a second power mode based on receiving the request and store a first address associated with a last information to be stored in the first portion of the memory system before the first portion entered the first power mode. In some cases, the memory system may enter the second power mode based on storing the first address, read the first address, and store data in a second address consecutively indexed after the first address based on reading the first address.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Zoltan Szubbocsev
  • Patent number: 11853170
    Abstract: A method, system and computer-readable storage medium for data backup by a backup server having local storage. In normal mode of operation the backup server stores any ingest data in the local storage. A redirect monitor continuously monitors the capacity utilization of the local storage. When the capacity utilization surpasses a preset threshold, the backup server is switched to operate in redirect mode, where newly received ingest data is redirected to alternate storage. The alternate storage may be, e.g., cloud storage or storage as a service facility. Thereafter the redirect monitor checks the utilization of the local storage and if that drops below a preset safety margin, the backup server reverts to normal operating mode. The backup server may or may not copy all redirected data from the alternate storage to the local storage, depending on the setup.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: December 26, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Jagannathdas Rath, Kalyan C. Gunda
  • Patent number: 11853578
    Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a component, such as a controller, for facilitating a transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may receive an indication of the data migration operation from a host device and may initiate a transfer of data between the first and second memory devices. The controller may include one or more buffers to store data being transferred between the first and second memory devices. In some cases, the transfer of data between the first and second memory devices may occur within the memory system and without being transferred through the host device.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: December 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
  • Patent number: 11853205
    Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: December 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
  • Patent number: 11847321
    Abstract: Disclosed herein are systems and method for adjusting storage volume size of an application instance. A method may include: identifying a first application instance running on a computing device, wherein the first application instance has an assigned first storage volume on a device storage of the computing device; collecting, over a period of time, usage data of the device storage; determining, based on the collected usage data, whether a usage capacity of the first storage volume of the first application instance is reaching a maximum capacity of the first storage volume; in response to determining that the usage capacity of the first storage volume is reaching the maximum capacity of the first storage volume, adjusting a size of the first storage volume by a first amount to accommodate usage of the first application instance.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: December 19, 2023
    Assignee: CLOUD LINUX SOFTWARE, INC.
    Inventors: Arsenii Pastushenko, Igor Seletskiy, Raushan Myrzashova
  • Patent number: 11847332
    Abstract: A data storage apparatus includes storage including a plurality of memory blocks and a controller configured to set an attribute of each of the memory blocks as a random memory block or a sequential memory block, and to manage validity of map data for data stored in each of the memory blocks using a map segment bitmap. The controller configures at least one memory block set by combining a set number of memory blocks, as a housekeeping event is triggered, and selects a victim block set from the at least one memory block set based on continuity of a logical address, or a number of valid map data, or both.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: December 19, 2023
    Assignee: SK hynix Inc.
    Inventors: Hye Mi Kang, Eu Joon Byun