Patents Examined by Midys Rojas
  • Patent number: 11249677
    Abstract: The present disclosure provides a method and an apparatus for erasing or writing Flash data. The method includes: reading an instruction for erasing or writing the data, the instruction for erasing or writing the data carrying start address information and end address information of a Flash memory where an operation of the instruction is to occur; querying whether the start address information and the end address information are in an address information table including one or more address ranges; and processing the instruction based on a result of the querying.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 15, 2022
    Assignee: C-SKY Microsystems Co., Ltd.
    Inventors: Yingjun Gao, Qijie Tong, Chunqiang Li, Han Mao
  • Patent number: 11237739
    Abstract: A memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory. The controller includes a processor, a storage circuit including a plurality of rewritable storage circuits that store timing data of a first timing information group which is settable by the processor, and a power source control circuit configured to trigger parallel execution of a plurality of power source control functions according to the timing data of the first timing information group read from the storage circuit.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: February 1, 2022
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshitaka Ikeda
  • Patent number: 11231885
    Abstract: The present disclosure generally relates to creating virtualized block storage devices whose data is replicated across isolated computing systems to lower risk of data loss even in wide-scale events, such as natural disasters. The virtualized device can include at least two volumes, each of which is implemented in a distinct computing system. Each volume can be implemented by at least two computing devices, a first of which is configured as a primary device to which reads from and writes to the volume are directed. To ensure consistency in the distributed device, a multi-tier authority service is implemented, in which a cross-computing system authority service designates a volume as having authority to accept writes to the virtualized device, and in which a second tier authority service designates a computing device as having authority to accept writes to the volume.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: January 25, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Kiran-Kumar Muniswamy-Reddy, Danny Wei, Norbert Paul Kusters, Romain Benoit Seguy, Rahul Upadhyaya, Divya Ashok Kumar Jain, William Zaharchuk, Wells Lin
  • Patent number: 11226905
    Abstract: An illustrative embodiment disclosed herein is an apparatus including a processor having programmed instructions to map a plurality of objects to a region and map the region to a plurality of vdisks. The plurality of objects are stored in the plurality of vdisks. The processor has programmed instructions to, responsive to mapping the plurality of objects to the region, identify a policy associated with the region. The policy specifies a policy action in response to satisfying a predetermined condition. The processor has programmed instructions to, responsive to satisfying the predetermined condition, access the plurality of vdisks and perform the policy action on the plurality of objects.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: January 18, 2022
    Assignee: Nutanix, Inc.
    Inventors: Karan Gupta, Gowtham Alluri, Dheer Moghe, Anshul Purohit, Arth Patel, Ajay Raghavan, Roger Liao
  • Patent number: 11221780
    Abstract: Implementations of the disclosure provide for size adjustable volumes for containers. A method of the disclosure includes determining, by a processing device of a Platform-as-a-Service (PaaS) system, a size limitation of a container, where the size limitation is associated with disk space usage of a storage volume group. The amount of disk space used by applications of the container is monitored in view of the size limitation of the container. Responsive to determining that the amount of the disk space used by the applications of the container satisfies a threshold, a storage volume of the storage volume group is allocated to the container in view of the size limitation of the container.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: January 11, 2022
    Assignee: Red Hat, Inc.
    Inventors: Daniel J. Walsh, Vivek Goyal, Shishir Mahajan
  • Patent number: 11204844
    Abstract: For accessing files from block-level backups of a virtual disk, a system, method, computer program product and apparatus are disclosed. The system includes an apparatus with a changed block module that determines changed blocks between a previous and a current block-level backup of a virtual disk. A mapping module maps logical clusters of the virtual disk to the changed blocks and identifies files corresponding to the logical clusters. A changed file module designates files corresponding to the logical clusters as changed files, unless current attributes of files for the current backup match attributes of the files in a backup file index corresponding to the previous backup. The changed file module stores the current attributes and extents for changed files within blocks of a backup storage device for updating in the backup file index. The method and computer program product perform these functions and may use the system and the apparatus.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: December 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Fruchtman, Avishai H. Hochberg, Vadzim I. Piletski, James P. Smith
  • Patent number: 11200172
    Abstract: A storage system includes a plurality of controllers and a plurality of storage drives. A first cache area and a second cache area are set in a memory. The first cache area is permitted to be written data by the plurality of storage drives, and the second cache area is not permitted to be written data by the plurality of storage drives. In a case where the plurality of controllers duplicates data stored in the cache area to a cache area of another controller for redundancy, the plurality of controllers causes the data to be redundant in a second cache area of the other controller in a case where the data is stored in the first cache area, and causes the data to be redundant in a first cache area of the other controller in a case where the data is stored in the second cache area.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: December 14, 2021
    Assignee: HITACHI, LTD.
    Inventors: Naoya Okada, Tomohiro Yoshihara, Takashi Nagao, Ryosuke Tatsumi
  • Patent number: 11200126
    Abstract: A method, apparatus and a product for utilizing translation tables for testing processors. The method is used for testing a target processor that utilizes different translation tables to translate virtual addresses to physical addresses. The method comprises obtaining a test template that comprises directives to be executed in different contexts, during each of which a different translation table is utilized to translate virtual addresses to physical addresses. The translation tables to be used by the target processor in the different contexts are determined, so that the translation tables overlap, at least in part.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Tom Kolan, Hillel Mendelson, Vitali Sokhin, Shay Aviv
  • Patent number: 11199979
    Abstract: One or more techniques and/or computing devices are provided for utilizing snapshots for data integrity validation and/or faster application recovery. For example, a first storage controller, hosting first storage, has a synchronous replication relationship with a second storage controller hosting second storage. A snapshot replication policy rule is defined to specify that a replication label is to be used for snapshot create requests, targeting the first storage, that are to be replicated to the second storage. A snapshot creation policy is created to issue snapshot create requests comprising the replication label. Thus a snapshot of the first storage and a replication snapshot of the second storage are created based upon a snapshot create request comprising the replication label. The snapshot and the replication snapshot may be compared for data integrity validation (e.g., determine whether the snapshots comprise the same data) and/or quickly recovering an application after a disaster.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: December 14, 2021
    Assignee: NetApp, Inc.
    Inventors: Pranab Patnaik, Akhil Kaushik
  • Patent number: 11194669
    Abstract: Methods and systems for improving data back-up, recovery, and search across different cloud-based applications, services, and platforms are described. A data management and storage system may direct compute and storage resources within a customer's cloud-based data storage account to back-up and restore data while the customer retains full control of their data. The data management and storage system may direct the compute and storage resources within the customer's cloud-based data storage account to generate and store secondary layers that are used for generating search indexes, to generate and store shared space layers and user specific layers to facilitate the deduplication of email attachments and text blocks, to perform a controlled restoration of email snapshots such that sensitive information (e.g., restricted keywords) located within stored snapshots remains protected, and to detect and preserve emails that were received or transmitted and then deleted between two consecutive snapshots.
    Type: Grant
    Filed: June 1, 2019
    Date of Patent: December 7, 2021
    Assignee: RUBRIK, INC.
    Inventors: Jal Jalali Ekram, David Anthony Terei
  • Patent number: 11188461
    Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to an estimated device age are discussed. An exemplary memory device includes a memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the wear-indicated device age relative to the actual device age.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: November 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Qing Liang, Deping He, David Aaron Palmer
  • Patent number: 11182090
    Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a component, such as a controller, for facilitating a transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may receive an indication of the data migration operation from a host device and may initiate a transfer of data between the first and second memory devices. The controller may include one or more buffers to store data being transferred between the first and second memory devices. In some cases, the transfer of data between the first and second memory devices may occur within the memory system and without being transferred through the host device.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: November 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
  • Patent number: 11163704
    Abstract: Disclosed is a method, apparatus, and/or computer program product for reducing latency in a processor with regard to the execution of noncacheable operations that includes receiving noncacheable operations from one or both of the level 2 cache and a level 3 cache, sending the noncacheable operations to a noncacheable unit (NCU) associated with a core of the processor, executing the noncacheable operations by the NCU, and sending results of the executed noncacheable operations to a host bridge for output to an input/out device. The noncacheable operations bypass the core of the processor.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventor: Shakti Kapoor
  • Patent number: 11163469
    Abstract: Provided is a data management system capable of properly managing data to undergo masking processing in the secondary use of data. This data storage management system is equipped with a storage unit which stores masked data of real data at a first point in time, and a data control unit which extracts data of a storage area that has not been masked from update data based on first information representing a masked storage area in the masked data and second information representing a masked storage area in the masked data of update data, which is data obtained by updating the real data from the first point in time to a second point in time, extracts data of the masked storage area, from which the same masked data has been removed, from the masked data of the update data, and generates the extracted data as difference data.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: November 2, 2021
    Assignee: HITACHI, LTD.
    Inventors: Kazuhiko Mizuno, Tsuyoshi Tanaka, Yohsuke Ishii
  • Patent number: 11152039
    Abstract: Methods, systems, and devices for input/output line sharing for memory subarrays are described. I/O lines may be shared across subarrays, which may correspond to separate memory tiles. The sharing of I/O lines may allow an I/O line to carry data from one subarray in response to access commands associated with one address range, and to carry data from another subarray in response to access commands associated with another address range. In some cases, sense amplifiers and other components may also be shared across subarrays, including across subarrays in different banks. The sharing of I/O lines may, in some cases, support activating only a subset of subarrays in a bank when accessing data stored in the bank, which may provide power savings.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christophe Vincent Antoine Laurent, Andrea Martinelli
  • Patent number: 11144234
    Abstract: An apparatus includes: a memory; and a processor coupled to the memory, the processor being configured to execute an access processing that includes making access to a storage, execute a monitoring processing that includes monitoring a state of usage of the storage in given timing, and execute a control processing that includes changing an operating frequency of the processor performing the access processing according to a monitoring result of the monitoring processing.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: October 12, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Satoshi Imamura
  • Patent number: 11144367
    Abstract: Methods and systems for controlling writing to register files in a processing system having at least two execution pipelines are provided. Aspects include obtaining a micro operation for execution by an execution unit of a first pipeline in the processing system, wherein the micro operation includes writing data to a register file. Aspects also include determining whether the data will be accessed by an execution unit of a second pipeline in the processing system. Based on a determination that the data will only be accessed by the execution unit of the first pipeline, aspects include blocking writing of the data to a register file of the second pipeline.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: October 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard Joseph Branciforte, Gregory William Alexander, Avraham Ayzenfeld, Edward Thomas Malley, Jonathan Ting Hsieh, Gregory Miaskovsky
  • Patent number: 11138104
    Abstract: A method is described. The method includes tracking a logical saturation value for each of multiple streams having read and write commands directed to a mass storage device, wherein, a stream's logical saturation value is a measurement of how much of the stream's assigned storage resources of the mass storage device contains valid data. The method also includes repeatedly selecting for garbage collection whichever of the multiple streams has a lowest logical saturation value as compared to the other streams.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventor: Shirish Bahirat
  • Patent number: 11132132
    Abstract: A storage apparatus includes a first memory, which is nonvolatile, a first controller that controls the first memory, a wireless antenna, a second memory, which is operable based on power supplied from the wireless antenna, and a second controller that is operable based on the power supplied from the wireless antenna, and performs communication using the wireless antenna. When performing communication with an external apparatus using the wireless antenna, the second controller performs authentication of the external apparatus, and stores in the second memory an authentication result indicating whether the authentication succeeded or failed. If the authentication result indicates that the authentication succeeded, the second controller permits reading by the external apparatus of first data from the second memory by communication using the wireless antenna or writing by the external apparatus of second data to the second memory by communication using the wireless antenna.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: September 28, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Masaomi Teranishi, Keisuke Sato, Shuichi Sakurai, Masahiko Nakashima
  • Patent number: 11132146
    Abstract: Memory page table invalidations for multiple execution contexts (clients or guests) of a memory system are conventionally queued in a single physical command queue. The multiple execution contexts contend to access the queue, resulting in low performance. Instead of contending with other execution contexts to insert invalidation commands into a single physical command queue, a virtual interface and one or more virtual command queues are allocated to each guest. The execution contexts may simultaneously transmit invalidation commands for the memory system through their respective virtual interface. Additionally, each execution context may also transmit other (less often issued) commands through a hypervisor. Error handling and/or illegal access checks specific to invalidation commands that were previously performed by the hypervisor are now performed by the respective virtual interface(s).
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 28, 2021
    Assignee: NVIDIA Corporation
    Inventors: Kaushal Agarwal, Alexander E. Van Brunt