Patents Examined by Minh Loan Tran
  • Dielectric structures for nitride semiconductor devices
    Patent number: 10297456
    Abstract: A dielectric structure for a nitride semiconductor device and a method of forming the same. A semiconductor device includes at least one semiconductor layer. The at least one semiconductor layer includes a gallium nitride semiconductor material. The semiconductor device also includes an oxidized layer disposed over the at least one semiconductor layer. The oxidized layer includes an oxidized form of the gallium nitride semiconductor of the at least one semiconductor layer. A silicon oxide layer is disposed over the oxidized layer. A gate is disposed over the silicon oxide layer.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 21, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Bernard A. Alamariu, Omair I. Saadat, Tomas Apostol Palacios
  • Display device and method of manufacturing the same
    Patent number: 10290686
    Abstract: An aspect of the present invention is directed to a display device including: an array substrate arranged with a plurality of pixels each having a light-emitting element are arranged; a first resin layer covering the plurality of pixels and having a first surface subjected to an alignment process; polarizers disposed over the first surface and aligned according to the alignment process; and a counter substrate disposed over the first resin layer.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: May 14, 2019
    Assignee: Japan Display Inc.
    Inventor: Daisuke Kato
  • III-V heterojunction field effect transistor
    Patent number: 10283598
    Abstract: Disclosed is a novel III-V heterojunction field effect transistor comprising a substrate layer, a first semiconductor layer, a second semiconductor layer, a drain electrode, a source electrode, a gate electrode, a first dielectric layer, second dielectric layers and the like, wherein the first semiconductor layer has a greater bandgap compared with the second semiconductor layer, and the second semiconductor layer and the first semiconductor layer are combined to form a heterostructure. The thickness of the first semiconductor layer is not greater than the critical thickness of two-dimensional electron gas formed in a heterojunction channel, and thus natural 2DEG in the heterojunction channel is depleted. The novel III-V heterojunction field effect transistor has the advantages of being simple in structure, simple in preparation process, stable in performance, high in reliability and the like.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: May 7, 2019
    Assignee: Hangzhou Dianzi University
    Inventors: Zhihua Dong, Zhiqun Cheng, Guohua Liu, Huajie Ke
  • Manufacturing semiconductor-based multi-junction photovoltaic devices
    Patent number: 10283666
    Abstract: Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields, greater efficiency, and lower costs. Certain solar cells may be from a different manufacturing process and further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device. A multi-junction cell may include a back surface field layer, a tunneling junction layer, a first active cell, and a second active cell.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: May 7, 2019
    Assignee: EpiWorks, Inc.
    Inventors: David Ahmari, Swee Lim, Shiva Rai, David Forbes
  • Semiconductor structure, HEMT structure and method of forming the same
    Patent number: 10269949
    Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Chung Chang, Po-Chih Chen, Jiun-Lei Jerry Yu, Chun Lin Tsai
  • Bidirectional Zener diode
    Patent number: 10269987
    Abstract: A bidirectional Zener diode of the present invention includes a semiconductor substrate of a first conductivity type, a first electrode and a second electrode which are defined on the semiconductor substrate, and a plurality of diffusion regions of a second conductivity type, which are defined at intervals from one another on a surface portion of the semiconductor substrate, to define p-n junctions with the semiconductor substrate, and the plurality of diffusion regions include diode regions which are electrically connected to the first electrode and the second electrode, and pseudo-diode regions which are electrically isolated from the first electrode and the second electrode.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: April 23, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Hiroki Yamamoto
  • Microelectromechanical system device
    Patent number: 10266391
    Abstract: A microelectromechanical system (MEMS) device includes a processing die, a MEMS die and a plurality of wires. The MEMS die includes a substrate and a MEMS element. The substrate has a first surface, and the first surface includes a circuit and a plurality of first conductive contacts electrically connected with the circuit. The MEMS element has a second surface, a third surface and at least one second conductive contact, wherein the MEMS element is disposed on the first surface of the substrate with the second surface facing the substrate, and the at least one second conductive contact is disposed on the third surface of the MEMS element. The wires electrically connect the substrate and the MEMS element of the MEMS die to the processing die through the first conductive contacts and the second conductive contact respectively.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: April 23, 2019
    Assignee: MIRAMEMS SENSING TECHNOLOGY CO., LTD
    Inventors: I-Heng Chou, Li-Tien Tseng, Chih-Liang Kuo
  • Semiconductor device and manufacturing method thereof
    Patent number: 10263090
    Abstract: A method for fabricating a semiconductor device is provided including an opening in a gate electrode layer to form two spaced apart gate electrode layers. An oxidation or nitridation treatment is performed in a region between the two spaced apart gate electrode layers. A first insulating layer is formed in the opening between the two spaced apart gate electrode layers.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: April 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Han Lin, Shih-Chang Tsai, Wen-Shuo Hsieh, Te-Yung Liu
  • Method for manufacturing a semiconductor device where a plurality of layers including a semiconductor layer made of an oxide semiconductor are stacked to form a thin film transistor
    Patent number: 10256346
    Abstract: In a semiconductor device including a semiconductor layer made of an oxide semiconductor, occurrence of variance in the characteristics of TFTs is suppressed. In a manufacturing process of a semiconductor device (100) where a passivation film (17) is to be formed at an upper layer of a semiconductor layer (11) made of an oxide semiconductor, deposition conditions of the passivation film (17) are set such that the proportion of pure metal (the ratio of pure metal to all the components of the semiconductor layer (11)) at an interface of the semiconductor layer (11) to the passivation film (17) becomes higher than the proportion of pure metal in the bulk of the semiconductor layer (11).
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: April 9, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takao Saitoh, Yohsuke Kanzaki, Yutaka Takamaru, Keisuke Ide, Seiji Kaneko
  • Light emitting diode package having frame with bottom surface having two surfaces different in height
    Patent number: 10249805
    Abstract: A light emitting diode package can include a substrate; a light emitting diode on the substrate; an electrode electrically connected to the light emitting diode; a frame surrounding the light emitting diode and configured to reflect light emitted from the light emitting diode; and a hole formed to pass through the substrate and configured to connect both upper and bottom surfaces of the substrate, in which a top surface of the frame is higher than a top surface of the light emitting diode, a portion of the frame has an inclined inner surface, the frame includes at least one protruding portion protruding from an imaginary surface where the light emitting diode is disposed, a bottom surface of the at least one protruding portion contacts the substrate, the at least one protruding portion is outside of the light emitting diode, and the hole is vertically overlapped with the light emitting diode.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: April 2, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Wan Ho Kim
  • Photodetector
    Patent number: 10249836
    Abstract: A photodetector includes a substrate, an interdigital electrode layer and a photoactive layer. The interdigital electrode layer is located or sandwiched between the substrate and the photoactive layer. The interdigital electrode layer includes a first interdigital electrode and a second interdigital electrode. The first interdigital electrode and the second interdigital electrode are spaced from and staggered with each other.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 2, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hao-Ming Wei, Yang Wei, Kai-Li Jiang, Shou-Shan Fan
  • Solid-state imaging element and electronic device to improve quality of an image
    Patent number: 10236311
    Abstract: The present technology relates to a solid-state imaging element and an electronic device capable of improving image quality of the solid-state imaging element. The solid-state imaging element includes a photoelectric conversion unit adapted to photoelectrically convert incident light incident from a predetermined incident surface. Also, the solid-state imaging element includes a wire arranged on a bottom surface side that is an opposite surface of the incident surface of the photoelectric conversion unit, and formed with a protruding pattern on a surface facing the photoelectric conversion unit. The present technology can be applied to, for example, a solid-state imaging element such as a CMOS image sensor, and an electronic device including the solid-state imaging element.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: March 19, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Ryoji Suzuki, Hitoshi Moriya, Atsuhiro Ando, Atsushi Masagaki
  • Thermal impedance amplifier
    Patent number: 10236433
    Abstract: A thermal impedance amplifier includes: a resistive layer including: a resistance member; a first electrode in electrical communication with the resistance member; and a second electrode in electrical communication with the resistance member; a switch layer opposing the resistive layer and including: a switch member; a first switch electrode in electrical communication with the switch member; and a second switch electrode in electrical communication with the switch member, the switch member: switching from a first resistance to a second resistance in response to receiving phonons from the resistance member, being superconductive at the first resistance, and producing an amplified voltage in response to being at the second resistance; and a thermal conductor interposed between the resistance member and the switch member.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: March 19, 2019
    Assignee: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventors: Adam McCaughan, Varun Verma, Sonia Buckley, Sae Woo Nam
  • Organic light emitting diode device with different laminated structures
    Patent number: 10224379
    Abstract: An organic light emitting diode (OLED) display device is provided. The OLED device includes a substrate, a first light emitting unit and a second light emitting unit. The first light emitting unit is disposed on the substrate. The first light emitting unit includes a first organic light emitting layer, a second organic light emitting layer and a first charge generation unit. The first charge generation unit is located between the first organic light emitting layer and the second organic light emitting layer. The first organic light emitting layer and the second organic light emitting layer are respectively in contact with a top surface and a bottom surface of the first charge generation unit. The second light emitting unit is disposed on the substrate. The second light emitting unit includes a third organic light emitting layer, and the second light emitting unit does not include a charge generation unit.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: March 5, 2019
    Assignee: INNOLUX CORPORATION
    Inventor: Chun-Kai Lee
  • Semiconductor device and method of manufacturing the same
    Patent number: 10211221
    Abstract: Disclosed is a method of manufacturing a semiconductor device, including: forming a stacked structure including first material layers and second material layers alternately stacked on each other; forming a pillar passing through the stacked structure, the pillar including a protruding portion protruding above an uppermost surface of the stacked structure; forming a conductive layer surrounding the protruding portion of the pillar; and forming a conductive pattern in contact with the protruding portion of the pillar by oxidizing a surface of the conductive layer.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: February 19, 2019
    Assignee: SK Hynix Inc.
    Inventor: Wan Cheul Shin
  • Semiconductor light emitting device
    Patent number: 10211372
    Abstract: A semiconductor light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, sequentially stacked on a substrate along a first direction, and including an exposed region exposing the first conductivity-type semiconductor layer. A first contact electrode is in the exposed region, a second contact electrode is on the second conductivity-type semiconductor layer, and an insulating layer covers the light emitting structure. Separate electrode pads penetrate the insulating layer to be electrically connected to the first contact electrode and the second contact electrode. A side surface of at least one of the first and second electrode pads may extend to be coplanar with a side surface of the substrate along the first direction.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin Hwan Kim, Sung Joon Kim, Su Hyun Jo, Seung Hwan Lee, Tae Sung Jang
  • Capacitor structures, decoupling structures and semiconductor devices including the same
    Patent number: 10211282
    Abstract: Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Min Lee, Jongryul Jun, Eun A Kim, Jung-Bum Lim
  • Device and method for producing a device
    Patent number: 10204880
    Abstract: A device and a method for producing a device are disclosed. In an embodiment the device includes a first component, a second component and a connecting element directly arranged between the first component and the second component, wherein the connecting element includes at least a first metal, which is formed as an adhesive layer, a diffusion barrier and a component of a first phase and a second phase of the connecting element, wherein the adhesive layer is arranged on the first component and/or the second component, wherein the first phase and/or the second phase includes, besides the first metal, further metals different from the first metal, wherein a concentration of the first metal in the first phase is greater than a concentration of the first metal in the second phase, and wherein the connecting element includes a layer of a silicide of the first metal.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: February 12, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Barbara Behr, Mathias Wendt, Marcus Zenger
  • Three-dimensional memory device with driver circuitry on the backside of a substrate and method of making thereof
    Patent number: 10199326
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word lines located over a front side surface of a semiconductor substrate, memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film, drain regions contacting a respective vertical semiconductor channel, bit lines electrically connected to the respective drain regions, driver circuitry for the memory stack structures located on a backside of the semiconductor substrate, and electrically conductive paths vertically extending through the semiconductor substrate and electrically connecting nodes of the driver circuitry to respective word lines or bit lines.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: February 5, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Shingo Ohsaki
  • Semiconductor device and method of manufacturing the same
    Patent number: 10199391
    Abstract: A semiconductor device includes an under layer, a stacked body comprising a plurality of conductive layers and insulating layers alternately stacked one over the other in a stacking direction, above the insulating layer, a columnar portion extending into the stacked body in the stacking direction of the stacked body, and a graphene film between at least one of the conductive layers and adjacent insulating layers and between the at least one of the conductive layers and the columnar portion.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: February 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Taishi Ishikura, Atsunobu Isobayashi, Masayuki Kitamura, Akihiro Kajita