Patents Examined by Mohamed M Gebril
  • Patent number: 11681628
    Abstract: A first cache of a first IOA is detected storing an amount of data that satisfies a memory shortage threshold. A request for extra memory for the first IOA is transmitted. The request is sent in response to detecting that the first cache stores the amount of data that satisfies the memory shortage threshold. The request is transmitted to a plurality of IOAs of a computer system. A second cache of a second IOA is detected storing an amount of data that satisfies a memory dissemination threshold. Memory of the second cache is allocated to the first cache. The memory is allocated in response to the request and the amount of data in the second cache satisfying the memory dissemination threshold.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 20, 2023
    Assignee: International Business Machines Corporation
    Inventors: Clark A. Anderson, Adrian C. Gerhard, William J. Maitland, Jr.
  • Patent number: 11681466
    Abstract: Example storage systems, storage devices, and methods provide proactive management of storage operations to, for example, beneficially minimize bottlenecking, latency, and other issues. An example system has a storage pool with a first storage device and a second storage device, and a processor configured to generate a storage request including a storage command, include a command processing time constraint in the storage request, send the storage request to the first storage device, and receive, from the first storage device, a proactive response including an estimation for an execution of the storage command by the first storage device based on the command processing time constraint. The processor may then select a fallback mechanism for executing the storage command based on the proactive response.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 20, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy
  • Patent number: 11656992
    Abstract: A programmable switch receives a cache line request from a client of a plurality of clients on a network to obtain a cache line. One or more additional cache lines are identified based on the received cache line request and prefetch information. The cache line and the one or more additional cache lines are requested from one or more memory devices on the network. The requested cache line and the one or more additional cache lines are received from the one or more memory devices, and are sent to the client.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 23, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marjan Radi, Dejan Vucinic
  • Patent number: 11650742
    Abstract: A computer system stores metadata that is used to identify physical memory devices that store randomly-accessible data for memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. Stored metadata associates a first address range of the address space with a first memory device, and a second address range of the address space with a second memory device. The operating system manages processes running on the computer system by accessing the stored metadata. This management includes allocating memory based on the stored metadata so that data for a first process is stored in the first memory device, and data for a second process is stored in the second memory device.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth Marion Curewitz, Shivasankar Gunasekaran, Ameen D. Akel, Hongyu Wang, Justin M. Eno, Shivam Swami, Samuel E. Bradshaw
  • Patent number: 11640262
    Abstract: Systems and methods are disclosed including a memory component and a processing device, coupled to the memory component. The processing device can program a block of the memory component using a first type of memory cells storing a first number of bits per memory cell. The processing device can then determine that an amount of memory used of the memory component is greater than a capacity threshold. Responsive to determining that a frequency of access to the block meets a criterion, the processing device can then program the block using a second type memory cells storing a second number of bits per memory cell, wherein the second number of bits exceeds the first number of bits.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: May 2, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Mark A. Helm
  • Patent number: 11630578
    Abstract: An electronic system includes: a key value storage device, configured to transfer user data, the key value storage device including: a non-volatile memory array accessed by a key value address, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to reduce a number of copies of the user data in the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree, including a key value translation block, to access the user data.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 18, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sushma Devendrappa, James Liu, Changho Choi, Xiling Sun
  • Patent number: 11599418
    Abstract: Methods, systems and computer program products for maintaining components of networked nodes with distributed data dependencies are described. For example, in accordance with one or more embodiments, a method can comprise identifying, by a device comprising a processor, in a group of dependent nodes of a cluster of nodes, a first portion of the dependent nodes for which an update is implicated. The method can further comprise selecting, by the device, from the first portion, a second portion of the dependent nodes that are predicted to be able to be updated with the update without affecting access to data of the group of dependent nodes. Further, the method can comprise communicating, by the device, the update to the second portion of the dependent nodes.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 7, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mark Ranger, Michael Frank, David T Leimbach, Raymond Ramsden
  • Patent number: 11599302
    Abstract: A storage device, including a feature information database configured to store feature information about a memory device; and a machine learning module configured to select a machine learning model from a plurality of machine learning models the corresponding to an operation of the memory device based on the feature information, wherein the memory device is configured to operate according to the selected machine learning model.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: March 7, 2023
    Assignee: SAMSUNG ELECTRONIC CO., LTD.
    Inventors: Jeong Woo Lee, Chan Ha Kim, Kang Ho Roh, Kwang Woo Lee, Hee Won Lee
  • Patent number: 11593015
    Abstract: Data protection operations including verification operations are disclosed. Objects written to a cloud tier are verified without reading the objects out of the cloud. A translation map is used that allows a cloud verifier engine to compare a checksum of an object generated at an local tier with a checksum of the object as stored in the cloud tier. Mismatches are identified and corrective actions can be taken by reconstructing and rewriting the object to the cloud tier. Garbage collection may be prevented from reclaiming data associated with objects that have not been verified.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: February 28, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Kalyan C. Gunda, Jagannathdas Rath
  • Patent number: 11593014
    Abstract: One embodiment provides a computer implemented method of estimating replication completion time. The method includes creating a historical dataset of prior replication data; determining a set of replication parameters to consider; inputting the historical dataset and the set of replication parameters to a replication completion time estimator module; generating a replication completion time prediction based on the historical dataset and the set of replication parameters; and generating a confidence prediction corresponding to the replication completion time prediction.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: February 28, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Rahul Vishwakarma, Lu Chen, Jitendra Singh, Bing Liu
  • Patent number: 11561703
    Abstract: In an approach to adaptive tape calibration criteria based on the number of dead tracks, the number of rewrite occurrences for each dead track on a tape drive is determined. Responsive to detecting that a head is in a dead track state, the number of dead tracks is stored on the tape drive. A calibration threshold is determined, where the calibration threshold includes the number of dead track rewrites and the calibration reference value for a specific tape drive type. Responsive to the number of rewrite occurrences exceeding the calibration threshold while writing a data set, a calibration of the tape drive.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: January 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Tsuyoshi Miyamura, Keisuke Tanaka, Ernest Stewart Gale
  • Patent number: 11561698
    Abstract: A storage array that uses NVMEoF to interconnect compute nodes with NVME SSDs via a fabric and NVME offload engines implements flow control based on transaction latency. Transaction latency is the elapsed time between the send side completion message and receive side completion message for a single transaction. Counts of total transactions and over-latency-limit transactions are accumulated over a time interval. If the over limit rate exceeds a threshold, then the maximum allowed number of enqueued pending transactions is reduced. The maximum allowed number of enqueued pending transactions is periodically restored to a default value.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: January 24, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Jinxian Xing, Julie Zhivich, John Krasner
  • Patent number: 11561700
    Abstract: Load balancing may include: receiving I/O workloads of storage server entities that service I/O operations received for logical devices, wherein each logical device has an owner that is one of the storage server entities that processes I/O operations directed to the logical device; determining normalized I/O workloads corresponding to the I/O workloads of the storage server entities; determining, in accordance with utilization criteria, imbalance criteria and the normalized I/O workloads, whether to rebalance the I/O workloads of the storage server entities; and responsive to determining to rebalance the I/O workloads of the storage server entities, performing processing to alleviate a detected I/O workload imbalance between two storage server entities. The processing may include moving logical device from a first storage server entity to a second storage server entity; and transferring ownership of the logical device from the first to the second storage server entity.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: January 24, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Shaul Dar, Gajanan S. Natu, Vladimir Shveidel
  • Patent number: 11544107
    Abstract: A storage system and method for multiprotocol handling are provided. In one embodiment, a computing device is provided comprising a plurality of communication channels configured to communicate with a storage system, wherein a first communication channel has a faster data transfer speed than a second communication channel. The computing device also comprises a processor configured to determine a priority level of a command; send the command with an indication of its priority level to the storage system; in response to the command being a high-priority command, use the first communication channel for transferring data for the command; and in response to the command being a low-priority command, use the second communication channel for transferring data for the command. Other embodiments are provided.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: January 3, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Hitesh Golechchha, Dinesh Kumar Agarwal
  • Patent number: 11520488
    Abstract: A consistency group is defined to include a set of required devices on a set of storage systems. Write patterns on each of the required devices are monitored and write patterns on each of the other devices on the set of storage systems is monitored. Pairs of devices are formed, in which each pair includes one required device and one other device. Write patterns of the pairs of devices are compared to determine respective percentage coordinated write probabilities for pairs of devices. Write patterns of the pairs of devices are also compared to determine ratios of write operations for pairs of devices. A coordinate write probability above a threshold, or a determined ratio of write operations that occurs sufficiently frequently, is interpreted as an indication that one of the other devices should be included in the consistency group. A learning process is trained and used to analyze the write patterns.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: December 6, 2022
    Assignee: Dell Products, L.P.
    Inventors: Peter Callewaert, Dennis Trulli, Jr.
  • Patent number: 11520523
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. When a write command is received to write data to a zone, change log data is generated and stored in the RAM1, the previous delta data for the zone is copied from the RAM2 to the RAM1 to be updated with the change log data, and the updated delta data is copied to the RAM2. The delta data stored in the RAM2 is copied to the storage unit periodically. The controller tracks which delta data has been copied to the RAM2 and to the storage unit. During a power failure, the delta data and the change log data are copied from the RAM1 or the RAM2 to the storage unit.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: December 6, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel L. Helmick, Peter Grayson
  • Patent number: 11520696
    Abstract: Apparatus and method for managing metadata in a data storage device, such as a solid-state drive (SSD). In some embodiments, a non-volatile memory (NVM) includes a population of semiconductor memory dies. The dies are connected a number of parallel channels such that less than all of the semiconductor dies are connected to each channel. A controller circuit apportions the semiconductor memory dies into a plurality of die sets, with each die set configured to store user data blocks associated with a different user. A separate set of map data is generated to describe user data blocks stored to each die set. The controller circuit stores the respective sets of map data in the associated die sets so that no die set stores map data associated with a different die set. The die sets may be arranged in accordance with the NVMe (Non-Volatile Memory Express) specification.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 6, 2022
    Inventors: Steven S. Williams, Kyumsung Lee, David W. Claude
  • Patent number: 11494089
    Abstract: A distributed storage system having a plurality of nodes that include a first node that stores write data in a storage device, and a second node that stores a redundancy code of the write data. The first node is configured to select a second node, among the plurality of nodes, to store the redundancy code after receiving the write data; and send the write data to the selected second node. The second node is configured to receive and hold the write data, determine whether a prescribed starting condition is met asynchronously with reception of the write data, calculate the redundancy code and a plurality of pieces of data and store the redundancy code in the storage device if the prescribed starting condition is met, hold the write data until a prescribed deletion condition is met and delete the write data after the prescribed deletion condition is met.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: November 8, 2022
    Assignee: HITACHI, LTD.
    Inventor: Hiromichi Iwase
  • Patent number: 11487477
    Abstract: A memory system includes a non-volatile memory and a controller. The controller controls writing of data to the non-volatile memory or reading of data from the non-volatile memory, in response to a command from at least one host. The controller performs command fetching by calculating for each of a plurality of queues, a remaining processing amount, which is an amount of processing remaining for one or more commands previously fetched therefrom, selecting a queue based on the remaining processing amounts calculated for the plurality of queues, and fetching a new command from the selected queue.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: November 1, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Toru Katagiri
  • Patent number: 11474702
    Abstract: A memory system includes a controller, a buffer, and a nonvolatile memory including a plurality of blocks, wherein each of the blocks includes a plurality of pages and each of the pages includes a plurality of unit data portions. The controller is configured to carry out garbage collection by reading data from one or more pages of a target block of the garbage collection and selectively copying valid unit data portions included in the read data to another block, count a number of invalid unit data portions included in the read data, and accept, in the buffer, unit data portions from a host as write data, up to a number determined based on the counted number, during the garbage collection.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: October 18, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Shinichi Kanno